CONTACT AIR GAP FORMATION AND STRUCTURES THEREOF

• US 20200135591A1
• Filed: 10/07/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: YEONG, Sai-Hooi, LEE, Kai-Hsuan
• Granted Patent: US 10,971,408 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 2221/1063 Sacrificial or temporary thin dielectric films in openings in a dielectric
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/4991 comprising an air gap
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A method of forming a device includes providing a transistor having a gate structure and a source/drain structure adjacent to the gate structure. A cavity is formed along a sidewall surface of a contact opening over the source/drain structure. After forming the cavity, a sacrificial layer is deposited over a bottom surface and along the sidewall surface of the contact opening including within the cavity. A first portion of the sacrificial layer along the bottom surface of the contact opening is removed to expose a portion of the source/drain structure. A metal plug is then formed over the portion of the exposed source/drain structure. A remaining portion of the sacrificial layer is removed to form an air gap disposed between the metal plug and the gate structure. Thereafter, a seal layer is deposited over the air gap to form an air gap spacer.

Claims

1. A method of forming a semiconductor device, comprising:

providing a first transistor including a first gate structure and a source/drain structure adjacent to the first gate structure;

forming a cavity along a sidewall surface of a contact opening disposed over the source/drain structure;

after forming the cavity, depositing a sacrificial layer over a bottom surface and along the sidewall surface of the contact opening including within the cavity, wherein the cavity is filled with the sacrificial layer;

removing a first portion of the sacrificial layer along the bottom surface of the contact opening to expose a portion of the source/drain structure;

forming a contact feature over the portion of the exposed source/drain structure;

removing a remaining portion of the sacrificial layer to form an air gap disposed between the contact feature and the first gate structure; and

depositing a seal layer over the air gap to form an air gap spacer.

2. The method of claim 1, wherein the remaining portion of the sacrificial layer is removed using a selective etching process.

3. The method of claim 1, further comprising:

prior to forming the cavity, forming a polymer layer over the first gate structure, wherein the polymer layer overhangs the first gate structure and covers at least a portion of the sidewall surface of the contact opening.

4. The method of claim 3, wherein the forming the cavity includes performing a dry etching process at a tilt angle.

5. The method of claim 1, wherein the sacrificial layer has a first thickness along the sidewall surface of the contact opening that includes the cavity, wherein the sacrificial layer has a second thickness over the first gate structure, and wherein the first thickness is greater than the second thickness.

6. The method of claim 1, further comprising:

prior to removing the first portion of the sacrificial layer, forming a blocking layer over the sacrificial layer; and

removing the first portion of the sacrificial layer, and a first portion of the blocking layer, along the bottom surface of the contact opening to expose the portion of the source/drain structure.

7. The method of claim 1, further comprising:

after exposing the portion of the source/drain structure and prior to forming the contact feature, forming a silicide layer in contact with the portion of the exposed source/drain structure; and

forming the contact feature over the silicide layer.

8. The method of claim 1, wherein the forming the cavity along the sidewall surface of the contact opening increases a dimension of an exposed region of the source/drain structure.

9. The method of claim 1, further comprising:

forming a second transistor including a second gate structure, wherein the source/drain structure is disposed between and adjacent to each of the first and second gate structures.

10. The method of claim 1, wherein a first width of a middle portion of the air gap spacer is greater than a second width of a top or bottom portion of the air gap spacer.

11. A method, comprising:

providing a first transistor including a first gate structure, a second transistor including a second gate structure, a source/drain structure disposed between and adjacent to each of the first and second gate structures, and a contact opening disposed over the source/drain structure;

forming a first cavity in a first sidewall surface of the contact opening and a second cavity in a second sidewall surface of the contact opening;

depositing a sacrificial layer along the first sidewall surface and along the second sidewall surface including within the first cavity and the second cavity;

forming a contact feature over the source/drain structure, wherein the contact feature is disposed between the sacrificial layer along the first sidewall surface and the sacrificial layer along the second sidewall surface;

after forming the contact feature, removing the sacrificial layer from the first sidewall surface and the second sidewall surface to form a first air gap disposed between the contact feature and the first gate structure and a second air gap disposed between the contact feature and the second gate structure; and

depositing a seal layer over the first air gap and the second air gap to form air gap spacers adjacent to the contact feature.

12. The method of claim 11, further comprising:

prior to forming the first cavity and the second cavity, depositing a first polymer layer over the first gate structure and a second polymer layer over the second gate structure, wherein the first polymer layer overhangs the first gate structure and covers at least a first portion of a first sidewall surface of the contact opening, and wherein the second polymer layer overhangs the second gate structure and covers at least a second portion of a second sidewall surface of the contact opening.

13. The method of claim 12, wherein the forming the first cavity and the second cavity further includes etching a third portion of the first sidewall surface of the contact opening to form the first cavity, and etching a fourth portion of the second sidewall surface of the contact opening to form the second cavity.

14. The method of claim 11, further comprising:

after forming the first cavity and the second cavity and prior to forming the contact feature, depositing the sacrificial layer over a bottom surface and along the first sidewall surface and the second sidewall surface of the contact opening including within the first cavity and the second cavity; and

removing a first portion of the sacrificial layer along the bottom surface of the contact opening to expose a portion of the source/drain structure.

15. The method of claim 14, further comprising:

after exposing the portion of the source/drain structure and prior to forming the contact feature, forming a silicide layer in contact with the exposed portion of the source/drain structure; and

forming the contact feature over the silicide layer.

16. The method of claim 11, further comprising:

prior to forming the contact feature, forming a blocking layer over the sacrificial layer along the first sidewall surface and over the sacrificial layer along the second sidewall surface; and

forming the contact feature over the source/drain structure, wherein the contact feature is disposed between the blocking layer over the sacrificial layer along the first sidewall surface and the blocking layer over the sacrificial layer along the second sidewall surface.

17. The method of claim 11, wherein the sacrificial layer has a first thickness in an upper region of both the first sidewall surface and the second sidewall surface, wherein the sacrificial layer has a second thickness in a lower region of both the first sidewall surface and the second sidewall surface, wherein the lower region of the first sidewall surface includes the first cavity and the lower region of the second sidewall surface includes the second cavity, and wherein the first thickness is less than the second thickness.

18. A semiconductor device, comprising:

a gate structure and a source/drain structure adjacent to the gate structure;

a contact feature disposed over the source/drain structure and adjacent to the gate structure; and

an air gap spacer including a seal layer formed over a cavity, wherein the air gap spacer is disposed between the contact feature and the gate structure, and wherein the cavity includes a curved sidewall profile.

19. The semiconductor device of claim 18, further comprising:

a blocking layer disposed on a sidewall of the contact feature, wherein the blocking layer is disposed between the contact feature and the air gap spacer.

20. The semiconductor device of claim 18, further comprising:

a silicide layer in contact with the source/drain structure, wherein the contact feature is disposed over the silicide layer.