METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

• US 20200135593A1
• Filed: 08/27/2019
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: TAKISHITA, Hiroshi, KITAHARA, Kazuhiro, KAWANO, Ryouichi, KUBOUCHI, Motoyoshi
• Granted Patent: US 11,081,410 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 22/30 Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 27/0727 in combination with diodes, or capacitors or resistors
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/6609 Diodes
• CPC Class Codes: H01L 29/66136 PN junction diodes
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/8613 Mesa PN junction diodes

Abstract

A method of manufacturing a semiconductor device from a semiconductor wafer in which a plurality of semiconductor chips are formed. The method includes a first process of forming an active region on a first main surface side of the semiconductor wafer and a second process of forming a first process control monitor (PCM) on a second main surface side of the semiconductor wafer. The method further includes before the second process, a third process of forming a second PCM on the first main surface side of the semiconductor wafer. The first PCM and the second PCM are formed at an area located at the same position in a plan view of the semiconductor wafer.

Claims

1. A method of manufacturing a semiconductor device from a semiconductor wafer in which a plurality of semiconductor chips are formed, the method comprising:

laying out a plurality of chip areas for the semiconductor chips in the semiconductor wafer, the semiconductor wafer having a first main surface and a second main surface opposite to the first main surface;

forming a plurality of active regions in the plurality of chip areas, respectively; and

forming at the second main surface a first process control monitor (PCM) in a first area other than the chip areas in which the active regions are formed.

2. The method according to claim 1, further comprising

before forming the first PCM, forming at the first main surface of the semiconductor wafer a second PCM in a second area other than the chip areas in which the active regions are formed, wherein

the first area and the second area entirely overlap each other in a plan view of the semiconductor wafer.

3. The method according to claim 1, wherein the first PCM includes an evaluation portion, the method further comprising

concurrently performing an ion implantation by implanting ions at the first area to form the first PCM and at each of the chip areas of the second main surface of the semiconductor wafer to form a corresponding one of the active regions.

4. The method according to claim 3, wherein

forming a plurality of active regions includes performing a plurality of ion implantations in the plurality of active regions at the second main surface, and

only one of the plurality of ion implantations performed in the active regions at the second main surface is concurrently performed at the first area to form the evaluation portion.

5. The method according to claim 3, wherein

forming the plurality of active regions includes performing a plurality of ion implantations in the plurality of active regions at the second main surface, and

a combination of more than one ion implantation among the plurality of ion implantations performed in the active regions at the second main surface is concurrently performed at the first area to form the evaluation portion.

6. The method according to claim 1, wherein forming the first PCM includes forming a marker at the first area for identifying a position of the first PCM relative to an entire area of the second main surface of the semiconductor wafer.

7. The method according to claim 1, wherein

the first PCM includes a plurality of marker portions, and

forming the first PCM includes forming a first marker portion disposed, as viewed in a plan view of the semiconductor wafer, at a center position of the second main surface of the semiconductor wafer, and a second marker portion disposed, as viewed in a plan view of the semiconductor wafer, at a peripheral position of the second main surface of the semiconductor wafer.

8. The method according to claim 1, wherein

forming a plurality of active regions includes forming a first load electrode on the first main surface, and a second load electrode on the second main surface so that a current passes between the first load electrode and the second load electrode.

9. The method according to claim 8, wherein

forming a plurality of active regions includes forming at the first main surface a control electrode that controls the current passing between the first load electrode and the second load electrode.

10. A method of manufacturing a semiconductor device from a semiconductor wafer in which a plurality of semiconductor chips are formed, the method comprising:

laying out a plurality of chip areas for the semiconductor chips in the semiconductor wafer, the semiconductor wafer having a first main surface and a second main surface opposite to the first main surface;

performing at the first main surface of the semiconductor wafer, a plurality of forming steps for forming the active regions in the chip areas;

forming at the first main surface of the semiconductor wafer, a process control monitor (PCM) in a second area other than the chip areas in which the active regions are to be formed;

performing at the second main surface of the semiconductor wafer, a plurality of forming steps for forming the active regions in the chip areas; and

forming at the second main surface an other PCM in a first area other than the chip areas in which the active regions are formed.