SOLDER MASK DESIGN FOR DELAMINATION PREVENTION

• US 20200135602A1
• Filed: 10/31/2018
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: ZHANG, James, XU, YI, CAI, Yuhong
• Granted Patent: US 11,476,174 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2224/32054 being rectangular or square
• CPC Class Codes: H01L 2224/32057 in side view
• CPC Class Codes: H01L 2224/3207 of bonding interfaces, e.g. interlocking features
• CPC Class Codes: H01L 2224/32112 the layer connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/33181 On opposite sides of the body
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48147 with an intermediate bond, e.g. continuous wire daisy chain
• CPC Class Codes: H01L 2224/48228 the bond pad being disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/8349 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3142 Sealing arrangements between parts, e.g. adhesion promotors
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49894 Materials of the insulating layers or coatings
• CPC Class Codes: H01L 23/538 : the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates H05K takes precedence; manufacture or treatment H01L21/4846 ; mountings per se H01L23/12; materials H01L23/49866
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/35121 : Peeling or delaminating

Abstract

Embodiments described herein provide techniques for forming a solder mask having a repeating pattern of features formed therein. The repeating pattern of features can be conceptually understood as a plurality of groove structures formed in the solder mask. The solder mask can be included in a semiconductor package that comprises the solder mask over a substrate and a molding compound over the solder mask that conforms to the repeating pattern of features. Several advantages are attributable to embodiments of the solder mask described herein. One advantage is that the repeating pattern of features formed in the solder mask increase the contact area between the solder mask and the molding compound. Increasing the contact area can assist with increasing adherence and conformance of the molding compound to the solder mask. This increased adherence and conformance assists with minimizing or eliminating interfacial delamination.

Claims

1. A semiconductor package, comprising:

a substrate;

a solder mask over the substrate, the solder mask having a repeating pattern of features formed into the solder mask; and

a molding compound over the solder mask, the molding compound conforming to the repeating pattern of features.

2. The semiconductor package of claim 1, further comprising a die stack on the solder mask.

3. The semiconductor package of claim 2, wherein the die stack is attached to the solder mask with a die attach film and wherein the die attach film conforms to the repeating pattern of features.

4. The semiconductor package of claim 1, wherein the repeating pattern of features comprises a plurality of trenches formed into the solder mask.

5. The semiconductor package of claim 4, wherein a trench has sidewalls and a bottom wall.

6. The semiconductor package of claim 5, wherein the sidewalls are sloped sidewalls.

7. The semiconductor package of claim 5, wherein the sidewalls are substantially vertical sidewalls.

8. The semiconductor package of claim 5, wherein the bottom wall is a slanted bottom wall.

9. The semiconductor package of claim 5, wherein the bottom wall is a substantially horizontal bottom wall.

10. The semiconductor package of claim 1, wherein the repeating pattern of features comprises a plurality of curvilinear trenches formed into the solder mask.

11. The semiconductor package of claim 10, wherein a curvilinear trench has a curved surface.

12. A packaged system, comprising:

a semiconductor package on a printed circuit board, the semiconductor package comprising;

a stack of dies on a solder mask;

the solder mask over a substrate, the solder mask having a repeating pattern of features formed into the solder mask; and

a molding compound over the solder mask, the molding compound conforming to the repeating pattern of features.

13. The packaged system of claim 12, wherein the solder mask has a solder resist opening (SRO) formed therein.

14. The packaged system of claim 13, wherein an interconnect passes through the SRO to couple the stack of dies to the substrate.

15. The packaged system of claim 12, wherein a die attach film couples the stack of dies to the solder mask and wherein the die attach film conforms to the solder mask.

16. The packaged system of claim 12, wherein each feature is a groove structure formed in the solder mask.

17. The packaged system of claim 16, wherein each groove structure is a tapered trench.

18. The packaged system of claim 16, wherein each groove structure is a rectilinear trench.

19. The packaged system of claim 16, wherein each groove structure is a curvilinear trench.

20. A method of forming a semiconductor package, comprising forming a repeating pattern of features into a solder mask on a substrate.

21. The method of claim 20, wherein forming the repeating pattern of features into the solder mask on the substrate comprises:

applying a roller onto the solder mask, the roller having the repeating pattern, wherein the repeating pattern is transferred into the solder mask.

22. The method of claim 20, wherein forming the repeating pattern of features into the solder mask on the substrate comprises:

applying the solder mask onto the substrate by unwinding the solder mask from a roller having the repeating pattern formed thereon, wherein the repeating pattern is transferred into the solder mask.

23. The method of claim 20, wherein forming the repeating pattern of features into the solder mask on the substrate comprises:

lithographically patterning the solder mask to form the repeating pattern therein, wherein the solder mask is formed from a light sensitive material.

24. The method of claim 23, wherein the light sensitive material comprises a photoresist or a photoimageable dielectric.

25. The method of claim 20, wherein forming the repeating pattern of features into the solder mask on the substrate comprises:

pressing a stamp into the solder mask, the stamp having the repeating pattern, wherein the repeating pattern is transferred into the solder mask.