SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

• US 20200135604A1
• Filed: 10/29/2018
• Published: 04/30/2020
• Est. Priority Date: 10/29/2018
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: YEN, You-Lung
• Granted Patent: US 10,755,994 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/4832 Etching a temporary substrate after encapsulation process to form leads
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/49861 Lead-frames fixed on or encapsulated in insulating substrates H01L23/4985, H01L23/49805 take precedence
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

A semiconductor package structure includes a patterned conductive layer with a front surface, a back surface, and a side surface connecting the front surface and the back surface. The semiconductor package structure further includes a first semiconductor chip on the front surface and electrically connected to the patterned conductive layer, a first encapsulant covering at least the back surface of the patterned conductive layer, and a second encapsulant covering at least the front surface of the patterned conductive layer, the side surface being covered by one of the first encapsulant and the second encapsulant.

Claims

1. A semiconductor package structure, comprising:

a patterned conductive layer, having a front surface, a back surface, and a side surface connecting the front surface and the back surface;

a first semiconductor chip on the front surface and electrically connected to the patterned conductive layer;

a first encapsulant covering at least the back surface of the patterned conductive layer; and

a second encapsulant covering at least the front surface of the patterned conductive layer, the side surface being covered by one of the first encapsulant and the second encapsulant.

2. The semiconductor package structure of claim 1, wherein the first encapsulant comprises epoxy and fillers.

3. The semiconductor package structure of claim 1, further comprising a conductive element on the back surface of the patterned conductive layer and being surrounded by the first encapsulant.

4. The semiconductor package structure of claim 1, wherein the first encapsulant covers the back surface and the side surface of the patterned conductive layer.

5. The semiconductor package structure of claim 4, wherein a water absorption rate of the first encapsulant is less than or equal to 0.5%.

6. The semiconductor package structure of claim 4, a Young'"'"'s modulus of the first encapsulant is greater than or equal to 15 GPa.

7. The semiconductor package structure of claim 1, wherein a boundary interfaces the first encapsulant and the second encapsulant.

8. The semiconductor package structure of claim 1, wherein the patterned conductive layer comprises a core substrate.

9. The semiconductor package structure of claim 1, further comprising a second semiconductor chip on the back surface of the patterned conductive layer and electrically connected to the patterned conductive layer.

21. The semiconductor package structure of claim 1, wherein the patterned conductive layer comprises a plurality of conductive traces.

22. The semiconductor package structure of claim 21, wherein at least one of the conductive traces comprises a first sub-layer, a second sub-layer, and a conductive via electrically connecting the first sub-layer and the second sub-layer.

23. The semiconductor package structure of claim 1, wherein the first encapsulant and the second encapsulant comprise different materials.

24. The semiconductor package structure of claim 3, wherein the conductive element comprises a first portion surrounded by the first encapsulant and a second portion protruding from the first encapsulant.

25. The semiconductor package structure of claim 24, wherein the first portion is substantially coplanar with the first encapsulant.

26. The semiconductor package structure of claim 24, wherein the first portion comprises a conductive pillar.

10. A semiconductor substrate, comprising:

a patterned conductive layer, having a front surface, a back surface, and a side surface connecting the front surface and the back surface; and

an encapsulant covering the back surface and the side surface of the patterned conductive layer.

11. The semiconductor substrate of claim 10, wherein the patterned conductive layer comprise a first conductive layer, a second conductive layer, and a conductive via electrically connecting the first conductive layer and the second conductive layer.

12. The semiconductor substrate of claim 10, wherein the patterned conductive layer comprises a core substrate.

13. The semiconductor substrate of claim 10, further comprising a solder resist layer over the patterned conductive layer.

14. The semiconductor substrate of claim 10, further comprising a plurality of dielectric units, and the encapsulant filling a gap between adjacent dielectric units.

15-20. -20. (canceled)