SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

• US 20200135606A1
• Filed: 10/31/2018
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Pan, Chih-Chien, Kao, Chin-Fu, Cheng, Li-Hui, Lu, Szu-Wei
• Granted Patent: US 10,796,976 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05138 the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05186 with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05638 the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05684 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/06181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/13025 : the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13082 : Two-layer arrangements
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/14181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/17181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/26175 : Flow barriers
• CPC Class Codes: H01L 2224/2919 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32145 : the bodies being stacked
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/92125 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/147 : Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3157 : Partial encapsulation or coating mask layer used as insulation layer H01L21/31
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/50 : for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate

Abstract

A method of forming a semiconductor device includes attaching a first semiconductor device to a first surface of a substrate; forming a sacrificial structure on the first surface of the substrate around the first semiconductor device, the sacrificial structure encircling a first region of the first surface of the substrate; and forming an underfill material in the first region.

Claims

1. A method of forming a semiconductor device, the method comprising:

attaching a first semiconductor device to a first surface of a substrate;

forming a sacrificial structure on the first surface of the substrate around the first semiconductor device, the sacrificial structure encircling a first region of the first surface of the substrate; and

forming an underfill material in the first region.

2. The method of claim 1, wherein the first surface of the substrate has passive components attached thereto, wherein the sacrificial structure is formed between the passive components and the first semiconductor device.

3. The method of claim 1, wherein forming the sacrificial structure comprises:

dispensing a sacrificial material in liquid form or gel form on the first surface of the substrate around the first semiconductor device; and

curing the sacrificial material while the sacrificial material is being dispensed.

4. The method of claim 3, wherein curing the sacrificial material comprises performing an ultraviolet (UV) curing process or a thermal curing process.

5. The method of claim 4, wherein the sacrificial material is cured by the UV curing process, wherein forming the sacrificial structure comprises controlling a shape of the sacrificial structure by adjusting a UV dosage of the UV curing process.

6. The method of claim 3, wherein the sacrificial material comprises polymer, polyimide, or epoxy.

7. The method of claim 1, wherein the sacrificial structure keeps the underfill material within the first region, wherein regions of the first surface of the substrate other than the first region are free of the underfill material.

8. The method of claim 1, further comprising removing the sacrificial structure after forming the underfill material.

9. The method of claim 8, further comprising curing the underfill material before removing the sacrificial structure.

10. The method of claim 9, wherein after the curing, a fillet of the underfill material has an upper portion distal from the substrate, a lower portion contacting the substrate, and a middle portion between the upper portion and the lower portion, wherein a first width of the upper portion increases continuously as the upper portion extends toward the substrate, and the middle portion has a uniform second width.

11. The method of claim 10, wherein a third width of the lower portion changes continuously as the lower portion extends toward the substrate.

12. The method of claim 8, wherein removing the sacrificial structure comprises performing a wet etch process using an etchant that is selective to the sacrificial structure, wherein the sacrificial structure is formed of an acrylic polymer, and the etchant comprises potassium hydroxide.

13. A method of forming a semiconductor device, the method comprising:

bonding a first semiconductor device to a first area of an upper surface of a substrate, wherein the upper surface of the substrate has passive components bonded thereto proximate to the first area;

forming a dam structure on the upper surface of the substrate around the first area, the dam structure disposed between the first semiconductor device and the passive components, the dam structure protruding above the upper surface of the substrate;

dispensing an underfill material within perimeters of the dam structure; and

curing the dispensed underfill material.

14. The method of claim 13, further comprising removing the dam structure after the curing.

15. The method of claim 13, wherein forming the dam structure comprises:

dispensing a polymer material on the upper surface of the substrate around the first semiconductor device; and

curing the polymer material as the polymer material is being dispensed.

16. The method of claim 15, wherein the polymer material is cured by an ultraviolet (UV) curing process, wherein the method further comprises adjusting a UV dosage of the UV curing process to control a sidewall profile of the dam structure.

17-20. -20. (canceled)

21. A method of forming a semiconductor device, the method comprising:

bonding a first semiconductor device to a first side of a substrate;

depositing a sacrificial material on the first side of the substrate around the first semiconductor device;

curing the sacrificial material, wherein after the curing, the sacrificial material form a dam structure protruding above the first side of the substrate and around the first semiconductor device; and

forming an underfill material within boundaries of the dam structure and between the first semiconductor device and the substrate, wherein the underfill material is contained within the boundaries of the dam structure by the dam structure.

22. The method of claim 21, wherein curing the sacrificial material comprises curing the sacrificial material using an ultra-violet (UV) light, wherein curing the sacrificial material further comprises adjusting a sidewall profile of the dam structure by adjusting a dosage of the UV light.

23. The method of claim 21, further comprising removing the dam structure after forming the underfill material.

24. The method of claim 21, wherein the underfill material is formed to physically contact the dam structure, wherein after being formed, a fillet of the underfill material has a first portion distal from the substrate and a second portion between the first portion and the substrate, wherein a first width of the first portion increases continuously as the first portion extends toward the substrate, and a second width of the second portion is uniform.