SEMICONDUCTOR DEVICE

• US 20200135607A1
• Filed: 09/18/2019
• Published: 04/30/2020
• Est. Priority Date: 10/24/2018
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: TSUCHIYA, Keita, KARIYAZAKI, Shuuichi, KIKUCHI, Takashi, SUGIYAMA, Michiaki, TANUMA, Yusuke
• Granted Patent: US 11,049,786 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/3675 characterised by the shape of the housing
• CPC Class Codes: H01L 23/3737 Organic materials with or without a thermoconductive filler
• CPC Class Codes: H01L 23/40 Mountings or securing means for detachable cooling or heating arrangements heating H01L23/345; fixed by friction, plugs or springs
• CPC Class Codes: H01L 23/42 Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

The semiconductor device includes a wiring substrate, a first and second semiconductor chips, and the heat sink. The wiring substrate has a first surface. The first and second semiconductor chips are disposed on the first surface. The heat sink is disposed on the first surface so as to cover the first semiconductor chip. The heat sink has a second surface and the third surface opposite the first surface. The second surface faces the first surface. The heat sink has a first cut-out portion. The first cut-out portion is formed at a position overlapping with the second semiconductor chip in plan view, and penetrates the heat sink in a direction from the third surface toward the second surface. The second surface is joined to at least four corners of the first surface.

Claims

1. A semiconductor device, comprising:

a wiring substrate having a first surface;

a first semiconductor chip and a second semiconductor chip disposed on the first surface; and

a heat sink having a second surface which faces the first surface and a third surface opposite the second surface, and disposed over the first surface such that the heat sink is disposed on the first semiconductor chip,

wherein the heat sink has a first cut-out portion which is formed at a position overlapping the second semiconductor chip in plan view,

wherein the first cut-out portion penetrates the heat sink plate in a direction from the third surface toward the second surface, and

wherein the second surface of the heat sink is bonded to at least four corners of the first surface of the wiring substrate.

2. The semiconductor device of claim 1,

wherein the first semiconductor chip has a first upper surface opposite the first surface of the wiring substrate,

wherein the second semiconductor chip has a second upper surface opposite the first surface of the wiring substrate, and

wherein the second upper surface is located farther from the first surface of the wiring substrate than the first upper surface of the first semiconductor chip.

3. The semiconductor device according to claim 2, further comprising:

a first adhesive member bonding the first surface of the wiring substrate and the second surface of the heat sink; and

a second adhesive member bonding the first upper surface of the first semiconductor chip and the second surface of the heat sink,

wherein a thermal conductivity of the second adhesive member is greater than a thermal conductivity of the first adhesive member.

4. The semiconductor device of claim 3,

wherein the second upper surface of the second semiconductor chip is located farther from the first surface of the wiring substrate than the second surface of the heat sink bonded to the first upper surface of the first semiconductor chip.

5. The semiconductor device according to claim 4,

wherein the first semiconductor chip is a bare chip and the second semiconductor chip is sealed with resin.

6. The semiconductor device according to claim 5,

wherein a logic circuit is formed in the first semiconductor chip and a memory circuit is formed in the second semiconductor chip.

7. The semiconductor device according to claim 6,

wherein an amount of heat generated by the first semiconductor chip is greater than an amount of heat generated by the second semiconductor chip.

8. The semiconductor device of claim 1,

wherein a thickness of the heat sink is greater than a thickness of the first semiconductor chip.

9. The semiconductor device according to claim 1,

wherein a protruding portion protrudes from the second surface along a direction from the third surface toward the second surface is formed on an edge portion of the heat sink on the first cut-out portion side.

10. The semiconductor device according to claim 1, further comprising:

a third semiconductor chip disposed on the first surface;

wherein the heat sink further comprises a second cut-out portion;

wherein the second cut-out portion is formed at a position overlapping the third semiconductor chip in plan view; and

penetrates the heat sink in a direction from the third surface toward the second surface.

11. The semiconductor device according to claim 10,

wherein the first surface includes a first side extending in a first direction and a second side extending in a second direction intersecting the first direction,

wherein the second semiconductor chip is disposed between the first side and the first semiconductor chip in plan view, and

wherein the third semiconductor chip is disposed between the second side and the first semiconductor chip in plan view.

12. The semiconductor device according to claim 11,

wherein the first surface further includes a third side extending in the first direction and facing the first side, and a fourth side extending in the second direction and facing the second side,

wherein the second semiconductor chip is disposed at a position shifted from the center of the first side to the fourth side in the first direction, and

wherein the third semiconductor chip is disposed at a position shifted from the center of the second side to the third side in the second direction.

13. The semiconductor device according to claim 11,

wherein the first surface further includes a third side extending in the first direction and facing the first side, and a fourth side extending in the second direction and facing the second side,

wherein the heat sink has, in plan view, a fifth side along the first side, a sixth side along the second side, a seventh side along the third side, and an eighth side along the fourth side, and

wherein a distance between an end on the third side of the second semiconductor chip and an end on the seventh side of the first cut-out portion is greater than a distance between the fifth side and the first side.

14. The semiconductor device according to claim 1, further comprising:

a fourth semiconductor chip disposed on the wiring substrate;

wherein the heat sink further comprises a third cut-out portion,

wherein the third cut-out portion is formed at a position overlapping the fourth semiconductor chip in plan view, and penetrates the heat sink in a direction from the third surface toward the second surface,

wherein the first surface includes a first side extending in a first direction;

a third side extending in the first direction and opposite the first side;

wherein the second semiconductor chip is disposed between the first side and the first semiconductor chip in plan view; and

wherein the fourth semiconductor chip is disposed between the third side and the first semiconductor chip in plan view.

15. The semiconductor device according to claim 1, further comprising:

a third semiconductor chip disposed on the first surface;

wherein the first surface includes a first side extending in a first direction; and

wherein the first cut-out portion is formed so as to overlap the second semiconductor chip and the third semiconductor chip in plan view.