ION THROUGH-SUBSTRATE VIA

• US 20200135617A1
• Filed: 04/23/2019
• Published: 04/30/2020
• Est. Priority Date: 10/24/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Shen, Yu-Yang, Tseng, Chien-Hsien, Yaung, Dun-Nian, Cheng, Nai-Wen, Chen, Pao-Tung
• Granted Patent: US 10,867,891 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/09181 On opposite sides of the body
• CPC Class Codes: H01L 2224/09517 including bonding areas providing primarily mechanical support
• CPC Class Codes: H01L 2224/80895 between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/80896 between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53214 the principal metal being aluminium
• CPC Class Codes: H01L 23/53228 the principal metal being copper
• CPC Class Codes: H01L 24/08 of an individual bonding area
• CPC Class Codes: H01L 24/80 Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14627 : Microlenses
• CPC Class Codes: H01L 27/14634 : Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/1464 : Back illuminated imager structures
• CPC Class Codes: H01L 27/14643 : Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/1469 : Assemblies, i.e. hybrid integration
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H10K 39/32 : Organic image sensors

Abstract

Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a first through substrate via (TSV) within a first semiconductor substrate. The first semiconductor substrate has a front-side surface and a back-side surface respectively on opposite sides of the first semiconductor substrate. The first semiconductor substrate includes a first doped channel region extending from the front-side surface to the back-side surface. The first through substrate via (TSV) is defined at least by the first doped channel region. A first interconnect structure on the front-side surface of the first semiconductor substrate. The first interconnect structure includes a plurality of first conductive wires and a plurality of first conductive vias, and the first conductive wires and the first conductive vias define a conductive path to the first TSV.

Claims

1. An integrated circuit (IC) comprising:

a first semiconductor substrate having a front-side surface and a back-side surface respectively on opposite sides of the first semiconductor substrate, wherein the first semiconductor substrate comprises a first doped channel region extending from the front-side surface to the back-side surface;

a first through substrate via (TSV) defined at least by the first doped channel region; and

a first interconnect structure on the front-side surface of the first semiconductor substrate, wherein the first interconnect structure comprises a plurality of first conductive wires and a plurality of first conductive vias, and wherein the first conductive wires and the first conductive vias define a conductive path to the first TSV.

2. The IC of claim 1, wherein the first semiconductor substrate comprises a second doped channel region and a third doped channel region respectively extending from the front-side surface to the back-side surface, wherein the second doped channel region is surrounded by the third doped channel region, and wherein the IC further comprises:

a second TSV defined at least by the second and third doped channel regions, wherein the first and third doped channel regions comprise a first doping type and the second doped channel region comprises a second doping type opposite the first doping type.

3. The IC of claim 2, wherein the first TSV and the second TSV are comprised of silicon and the first conductive wires and vias are comprised of copper or aluminum.

4. The IC of claim 2, further comprising:

a first isolation structure extending into the front-side surface of the first semiconductor substrate, wherein an outer sidewall of the first doped channel region adjoins an inner sidewall of the first isolation structure; and

a second isolation structure extending into the front-side surface of the first semiconductor substrate to an isolation-structure surface facing the back-side surface of the first semiconductor substrate, wherein an outer sidewall of the second doped channel region adjoins an inner sidewall of the second isolation structure, and wherein the isolation-structure surface adjoins the third doped channel region.

5. The IC of claim 1, wherein the first semiconductor substrate, the first interconnect structure, and the first TSV partially define a first IC die, and wherein the IC further comprises:

a second IC die underlying and bonded to the first IC die, wherein the second IC die comprises a second semiconductor substrate, a semiconductor device, and a second interconnect structure, wherein the semiconductor device overlies and is on the second semiconductor substrate, between the second semiconductor substrate and the second interconnect structure, and wherein the first TSV is electrically coupled to the semiconductor device through the first and second interconnect structures.

6. The IC of claim 5, further comprising:

a third IC die overlying and bonded to the first IC die, wherein the third IC die comprises a third semiconductor substrate, a photodetector, and a third interconnect structure, wherein the photodetector is in the third semiconductor substrate and overlies the first TSV, wherein the third interconnect structure is between the third semiconductor substrate and the first IC die, and wherein the photodetector is electrically coupled to the semiconductor device through the first TSV and the first, second, and third interconnect structures.

7. The IC of claim 6, wherein the first, second, and third interconnect structure each comprise an alternating stack of wires and vias, wherein the wires and the vias are comprised of metal, and wherein the first TSV is comprise of silicon.

8. The IC of claim 6, wherein the first TSV overlies the semiconductor device.

9. An integrated circuit (IC) comprising:

a first IC die comprising a first semiconductor substrate and a first interconnect structure overlying the first semiconductor substrate;

a second IC die over the first IC die, wherein the second IC die comprises a second semiconductor substrate and a second interconnect structure underlying the second semiconductor substrate, and wherein the first and second IC dies contact at a bond interface between the first and second interconnect structures;

a plurality of semiconductor devices on the first semiconductor substrate and/or the second semiconductor substrate; and

a first through-substrate via (TSV) and a second TSV within the second semiconductor substrate and electrically coupled to the first interconnect structure through the second interconnect structure, and wherein the first and second TSVs and the second semiconductor substrate are comprised of a semiconductor material.

10. The IC according to claim 9, wherein the first and second interconnect structures are comprised of a conductive material different than the semiconductor material.

11. The IC according to claim 10, wherein the semiconductor material comprises silicon and the conductive material comprises copper.

12. The IC according to claim 9, wherein a maximum width of the first TSV is less than a minimum width of the second TSV.

13. The IC according to claim 9, wherein the second semiconductor substrate comprises a first doping type, wherein the first TSV comprises a second doping type opposite the first doping type, wherein the second TSV comprises and inner region surrounded by an outer region, and wherein the inner region comprises the first doping type and the outer region comprises the second doping type.

14. The IC according to claim 13, wherein the inner region comprises a higher doping concentration of the first doping type than the second semiconductor substrate.

15. The IC according to claim 9, further comprising:

a first isolation structure extending from a front-side surface of the second semiconductor substrate to a position in the second semiconductor substrate, wherein an outer sidewall of the first TSV adjoins an inner sidewall of the first isolation structure; and

a second isolation structure extending from the front-side surface of the second semiconductor substrate to an isolation-structure surface of the second isolation structure, wherein the isolation-structure surface is at the position and adjoins the second TSV.

16. A method for forming an integrated circuit (IC), the method comprising:

performing an ion implant process into a front-side surface of a first semiconductor substrate to form a first doped channel region extending into the first semiconductor substrate from the front-side surface;

forming a first interconnect structure on the front-side surface of the first semiconductor substrate;

thinning the first semiconductor substrate from a back-side surface of the first semiconductor substrate until the first doped channel region is exposed, wherein the back-side surface is opposite the front-side surface of the first semiconductor substrate; and

forming a conductive pad overlying and electrically coupled to the first doped channel region on the back-side surface of the first semiconductor substrate.

17. The method according to claim 16, further comprising:

forming an isolation structure around the first doped channel region.

18. The method according to claim 16, wherein the ion implant process further comprises:

forming a second doped channel region in the first semiconductor substrate and laterally offset from the first doped channel region, wherein the first and second doped channel regions comprise a first doping type;

forming a third doped channel region in the first semiconductor substrate, wherein the third doped channel region comprises a second doping type opposite the first doping type and an outer sidewall of the third doped channel region adjoins an inner sidewall of the second doped channel region; and

performing a rapid thermal anneal (RTA) process.

19. The method according to claim 18, wherein the first doping type is n-type and the second doping type is p-type, and wherein the RTA process has a maximum temperature of approximately 1010 degrees Celsius.

20. The method according to claim 16, further comprising:

bonding the first interconnect structure to a second interconnect structure of a logic IC die, wherein the logic IC die comprises a second semiconductor substrate underlying the second interconnect structure, and wherein at least one semiconductor device is disposed on the second semiconductor substrate and underlies the first doped channel region.