LEADS FOR LEADFRAME AND SEMICONDUCTOR PACKAGE

• US 20200135621A1
• Filed: 07/17/2019
• Published: 04/30/2020
• Est. Priority Date: 10/24/2018
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: HOW, YOU CHYE, BIN ABDUL AZIZ, ANIS FAUZI
• Granted Patent: US 11,830,791 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/28 Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
• CPC Class Codes: H01L 2021/60015 using plate connectors, e.g. layer, film
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/49513 having bonding material between chip and die pad
• CPC Class Codes: H01L 23/49534 Multi-layer
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 23/49548 Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49555 the bent parts being the outer leads
• CPC Class Codes: H01L 23/49558 Insulating layers on lead frames, e.g. bridging members
• CPC Class Codes: H01L 23/49582 Metallic layers on lead frames
• CPC Class Codes: H02H 3/42 responsive to product of voltage and current
• CPC Class Codes: H02H 5/042 using temperature dependent resistors
• CPC Class Codes: H02H 5/047 using a temperature responsive switch
• CPC Class Codes: H02H 6/00 Emergency protective circuit arrangements responsive to undesired changes from normal non-electric working conditions using simulators of the apparatus being protected, e.g. using thermal images
• CPC Class Codes: H02H 7/222 for switches
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A semiconductor package includes a die pad and leads extending from the die pad. Each lead has a free end with outer surfaces extending at angles from one another. An electrically conductive plating material covers at least portions of the outer surfaces. A die attached to the die pad is electrically connected to the leads. An insulating layer extends over the leads and the die such that the free ends of the leads are exposed.

Claims

1. A semiconductor package, comprising:

a die pad;

leads extending from the die pad each having a free end with outer surfaces extending at angles from one another;

an electrically conductive plating material covering at least portions of the outer surfaces;

a die attached to the die pad and electrically connected to the leads; and

an insulating layer extending over the leads and the die such that the free ends of the leads are exposed.

2. The semiconductor package recited in claim 1, wherein the electrically conductive plating material comprises tin.

3. The semiconductor package recited in claim 1, wherein each lead is rectangular and the outer surfaces comprise opposing first and second surfaces and opposing third and fourth surfaces, the electrically conductive plating material covering the first and second surfaces and at least partially covering the third and fourth surfaces.

4. The semiconductor package recited in claim 3, wherein the plating material covers half of the third surface and half of the fourth surface.

5. The semiconductor package recited in claim 1, wherein the plating material wraps around the outer surfaces.

6. The semiconductor package recited in claim 1, wherein the leads extend in the same plane as one another.

7. The semiconductor package recited in claim 1, wherein the free ends have a length of about 0.1 mm to about 0.3 mm.

8. A method of manufacturing a semiconductor package, comprising the steps of:

providing a lead frame having a die pad and leads extending from the die pad to a dam bar, the leads having a first thickness and outer surfaces extending at angles from one another, the dam bar having a first portion having the first thickness and a second portion having a second thickness less than the first thickness to form a cavity;

attaching a die to the die pad;

electrically connecting the die to the leads;

overmolding the lead frame with an electrically insulating material that fills the cavity and leaves free ends of the leads exposed;

removing the electrically insulating material from the cavity;

plating the overmolded lead frame with an electrically conductive material that covers at least portions of the outer surfaces; and

removing the dam bar.

9. The method recited in claim 8, wherein the electrically conductive plating material comprises tin.

10. The method recited in claim 8, wherein each lead is rectangular and the outer surfaces comprise opposing first and second surfaces and opposing third and fourth surfaces, the electrically conductive plating material covering the first and second surfaces and at least partially covering the third and fourth surfaces.

11. The method recited in claim 10, wherein the entirety of the first and second surfaces are exposed following overmolding and prior to removing the electrically insulating material from the cavity.

12. The method recited in claim 8, wherein plating the overmolded lead frame with an electrically conductive material covers half of the third surface and half of the fourth surface.

13. The method recited in claim 8, wherein plating the overmolded lead frame with an electrically conductive material wraps the plating around the outer surfaces.

14. The method recited in claim 8, wherein the leads extend in the same plane as one another.

15. The method recited in claim 8, wherein the free ends have a length of about 0.1 mm to about 0.3 mm.