SEMICONDUCTOR PACKAGE HAVING DIE PAD WITH COOLING FINS

• US 20200135625A1
• Filed: 10/16/2019
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: TALLEDO, Jefferson
• Granted Patent: US 11,398,417 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/4828 Etching etching for cleaning without patterning H01L21/4835
• CPC Class Codes: H01L 21/4871 Bases, plates or heatsinks
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/29298 Fillers
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48106 the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83101 as prepeg comprising a layer connector, e.g. provided in an insulating plate member
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49513 having bonding material between chip and die pad
• CPC Class Codes: H01L 23/49531 the additional leads being a wiring board
• CPC Class Codes: H01L 23/49541 : Geometry of the lead-frame
• CPC Class Codes: H01L 23/49548 : Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49568 : specifically adapted to facilitate heat dissipation
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18301 : being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

Abstract

Embodiments of the present disclosure are directed to leadframe semiconductor packages having die pads with cooling fins. In at least one embodiment, the leadframe semiconductor package includes leads and a semiconductor die (or chip) coupled to a die pad with cooling fins. The cooling fins are defined by recesses formed in the die pad. The recesses extend into the die pad at a bottom surface of the semiconductor package, such that the bottom surfaces of the cooling fins of the die pad are flush or coplanar with a surface of the package body, such as an encapsulation material. Furthermore, bottom surfaces of the cooling fins of the die pad are flush or coplanar with exposed bottom surfaces of the leads.

Claims

1. A semiconductor package, comprising:

a die pad having first and second opposing surfaces, the second surface of the die pad including a plurality of recesses and a plurality of cooling fins;

a semiconductor die coupled to the first surface of the die pad;

a plurality of leads;

a plurality of conductive wires, the semiconductor die electrically coupled to the plurality of leads by the plurality of conductive wires, respectively; and

encapsulation material over the first surface of the die pad, the semiconductor die, and the plurality of conductive wires,

wherein an outer surface of the encapsulation material is flush with surfaces of the plurality of leads, and surfaces of the plurality of cooling fins to form a coplanar outer surface of the package.

2. The semiconductor package of claim 1, wherein the die pad has a thickness of at least 0.25 millimeters.

3. The semiconductor package of claim 2, wherein the plurality of leads have a same thickness as the die pad.

4. The semiconductor package of claim 1, wherein the recesses extend more than 50% through a thickness of the die pad.

5. The semiconductor package of claim 1, wherein the cooling fins and recesses are arranged in alternating columns at the second surface of the die pad.

6. The semiconductor package of claim 1, wherein the plurality of leads have first surfaces exposed at a first surface of the package and second surfaces exposed at a second surface of the package, wherein the first surface of the package opposes the second surface of the package.

7. The semiconductor package of claim 6, wherein the second surfaces of the plurality of leads are coupled to conductive pads of a PCB, wherein the cooling fins face away from the PCB.

8. The semiconductor package of claim 1, wherein the first surfaces of the plurality of leads are coupled to conductive pads of a PCB, wherein at least some of the cooling fins of the die pad are coupled to the PCB.

9. The semiconductor package of claim 8, wherein portions of the cooling fins at a perimeter of the die pad are coupled to the PCB.

10. An electronic device, comprising:

a printed circuit board; and

a semiconductor package coupled to the printed circuit board, the semiconductor package including;

a die pad having first and second opposing surfaces, the second surface of the die pad including a cooling fin;

a semiconductor die coupled to the first surface of the die pad;

a lead, the semiconductor die electrically coupled to the lead; and

encapsulation material coving the first surface of the die pad and the semiconductor die,

wherein a surface of the encapsulation material is coplanar with a first surface of the lead, and a surface of the cooling fin to form an outer surface of the semiconductor package.

11. The electronic device of claim 10, wherein the first surface of the lead is coupled to a conductive pad of a PCB.

12. The electronic device of claim 11, wherein a second surface of the lead is coupled to the conductive pad of the PCB, wherein the second surface and the first surface of the lead are on opposing sides.

13. The electronic device of claim 10, wherein the cooling fin is formed by a recess that extends at least 50% of a thickness of the die pad.

14. The electronic device of claim 10, wherein the die pad has a thickness of at least 0.25 millimeters.

15. A method, comprising:

forming at least one recess in a first surface of a die pad to form a cooling fin;

coupling a semiconductor die to a second surface of the die pad;

electrically coupling the semiconductor die to a plurality of leads; and

encapsulating the semiconductor die in a packaging material to form a semiconductor package,

wherein the semiconductor package has an outer coplanar surface that includes the packaging material, a surface of the cooling fin, and surfaces of the plurality of leads.

16. The method of claim 15, wherein forming the at least one recess comprises forming a plurality of recesses in the first surface of the die pad to form a plurality of cooling fins.

17. The method of claim 16, wherein the step of forming the plurality of recesses occurs after the step of encapsulating the semiconductor die in the packaging material.

18. The method of claim 16, wherein forming the plurality of recesses comprises etching to at least 50% of a thickness of the die pad to form the plurality of cooling fins.

19. The method of claim 16, wherein the plurality of recesses are arranged in columns to form a plurality of cooling fins arranged in columns that alternate with the plurality of recesses.

20. The method of claim 16, further comprising coupling the semiconductor package to a PCB, wherein the plurality of cooling fins face away from the PCB.