SUBSTRATES WITH SOLDER BARRIERS ON LEADS

• US 20200135627A1
• Filed: 10/30/2018
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Application

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: GALLEGOS, Bernardo, KOZIOL, Madison
• Application Number:
  US16/175,279
• Publication Number:
  US 20200135627A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 2224/10175 Flow barriers
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 23/4951 Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49572 consisting of thin flexible metallic tape with or without a film carrier H01L23/49503 - H01L23/49568 and H01L23/49575 - H01L23/49579 take precedence
• CPC Class Codes: H01L 23/49582 Metallic layers on lead frames
• CPC Class Codes: H01L 23/49586 Insulating layers on lead frames
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/15151 the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections

Abstract

A system comprises a substrate. The substrate comprises a lead. The system also comprises a solder barrier formed on the lead. The solder barrier is to contain a solder bump within a solder area on the lead. The system further includes a solder bump in the solder area and a die having an active surface coupled to the solder bump.

Claims

1. A system comprising:

a substrate, the substrate comprising a lead;

a solder barrier formed on the lead, the solder barrier to contain a solder bump within a solder area on the lead;

a solder bump in the solder area; and

a die having an active surface coupled to the solder bump.

2. The system of claim 1, wherein the solder barrier comprises a resin.

3. The system of claim 1, further comprising a plating finish on the lead, wherein the solder barrier is formed on the plating finish.

4. The system of claim 1, wherein the solder barrier comprises metallic dots.

5. The system of claim 1, further comprising:

a mold compound formed over at least a portion of the substrate.

6. The system of claim 1, wherein the die comprises an integrated circuit electrically coupled to the lead.

7. The system of claim 1, wherein the lead comprises copper.

8. The system of claim 1, further comprising a plating finish on the lead, the plating finish comprising nickel and palladium.

9. The system of claim 8, the plating finish further comprising a metal, the metal selected from the group consisting of silver and gold.

10. A method comprising:

plating a lead of a substrate for solder wettability to provide a plated lead; and

forming a solder barrier on the plated lead, the solder barrier having a structure to contain solder reflow within a solder area on the plated lead.

11. The method of claim 10, wherein the substrate comprises copper.

12. The method of claim 10, wherein plating the lead comprises plating the lead with nickel and palladium.

13. The method of claim 12, wherein plating the lead further comprises plating the lead with metal selected from the group consisting of gold and silver.

14. The method of claim 10, further comprising:

forming a mold compound in contact with the lead.

15. The method of claim 10, further comprising:

soldering a solder bump to electrically couple an active surface of a die to the solder area.

16. The method of claim 10, wherein forming the solder barrier on the plated lead comprises:

depositing resin on the plated lead.

17. The method of claim 10, wherein forming the solder barrier on the plated lead comprises:

depositing metallic dots on the plated lead.

18. A semiconductor package comprising:

a lead comprising a metal;

a surface plating on the lead;

a solder barrier on the surface plating to define a solder area; and

a die having an active surface coupled to the solder area via a solder bump.

19. The semiconductor package of claim 18, wherein:

the metal comprises copper; and

the surface plating comprises nickel and palladium.

20. The semiconductor package of claim 18, wherein the solder barrier comprises a resin.