SEMICONDUCTOR PACKAGE

• US 20200135636A1
• Filed: 06/25/2019
• Published: 04/30/2020
• Est. Priority Date: 10/24/2018
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: LEE, Hyuek Jae, KIM, Ji Hoon, KIM, Tae Hun, HONG, Ji Seok, HWANG, Ji Hwan
• Granted Patent: US 11,056,432 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/08 of an individual bonding area
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/08225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/73251 on different surfaces
• CPC Class Codes: H01L 2224/80 Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 2224/80091 Under pressure
• CPC Class Codes: H01L 2224/80097 Heating
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/95001 involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
• CPC Class Codes: H01L 2224/95091 Under pressure
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/473 : by flowing liquids H01L23/4332, H01L23/4338 take precedence
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 29/0657 : characterised by the shape of the body
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/10156 : at the periphery
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA

Abstract

A semiconductor package is provided. The semiconductor package includes a lower structure including an upper insulating layer and an upper pad; and a semiconductor chip provided on the lower structure and comprising a lower insulating layer and a lower pad. The lower insulating layer is in contact with and coupled to the upper insulating layer and the lower pad is in contact with and coupled to the upper pad, and a lateral side of the semiconductor chip extends between an upper side and a lower side of the semiconductor chip and comprises a recessed portion.

Claims

1. A semiconductor package comprising:

a lower structure comprising an upper insulating layer and an upper pad; and

a semiconductor chip provided on the lower structure and comprising a lower insulating layer and a lower pad,

wherein the lower insulating layer is in contact with and coupled to the upper insulating layer and the lower pad is in contact with and coupled to the upper pad, and

wherein a lateral side of the semiconductor chip extends between an upper side and a lower side of the semiconductor chip and comprises a recessed portion.

2. The semiconductor package of claim 1, wherein the lateral side of the semiconductor chip further comprises a first portion extending from the upper side to the recessed portion in a first direction that is substantially perpendicular to the upper side, and

wherein the recessed portion extends from the lower side to the first portion.

3. The semiconductor package of claim 2, wherein the recessed portion comprises a vertical portion and a curved portion,

wherein the vertical portion extends from the lower side in a second direction that is substantially perpendicular to the lower side, and

wherein the curved portion extends from the vertical portion to the first portion.

4. The semiconductor package of claim 1, wherein the lower structure is wider than the semiconductor chip.

5. The semiconductor package of claim 1, wherein the semiconductor chip further comprises a semiconductor body and a semiconductor internal circuit region interposed between the semiconductor body and both of the lower insulating layer and the lower pad.

6. The semiconductor package of claim 5, wherein the semiconductor internal circuit region is narrower than the upper side of the semiconductor chip.

7. The semiconductor package of claim 1, wherein the lower structure further comprises a lower body and a lower internal circuit region is interposed between the lower body and both of the upper insulating layer and the upper pad.

8. The semiconductor package of claim 1, wherein the lower structure further comprises a lower body and a lower internal circuit area interposed between the lower internal circuit area and both of the upper insulating layer and the upper pad.

9. The semiconductor package of claim 1, wherein the lower structure further comprises a lower body and a penetrating electrode, and

wherein the penetrating electrode is electrically connected to the upper pad and penetrates through the lower body.

10. The semiconductor package of claim 9, wherein the lower body comprises a silicon substrate.

11. The semiconductor package of claim 1, further comprising a molding layer that is provided on the lower structure and covers the lateral side of the semiconductor chip.

12. The semiconductor package of claim 11, further comprising a heat dissipation structure provided on the molding layer and the semiconductor chip.

13. A semiconductor package comprising:

a lower structure; and

a semiconductor chip provided on the lower structure and having an upper side a lower side that opposes the upper side,

wherein the lower structure comprises an upper pad and an upper insulating layer,

wherein the semiconductor chip comprises a lower pad and a lower insulating layer that are provided at the lower side of the semiconductor chip,

wherein the lower pad is in contact with and coupled to the upper pad,

wherein the lower insulating layer is in contact with and coupled to the upper insulating layer, and

wherein the lower side of the semiconductor chip is narrower than the upper side of the semiconductor chip.

14. The semiconductor package of claim 13, further comprising a molding layer disposed on a lateral side of the semiconductor chip extending between the upper side and the lower side.

15. The semiconductor package of claim 14, wherein a first portion of the upper insulating layer is in contact with the lower insulating layer, and a second portion of the upper insulating layer is in contact with the molding layer.

16. The semiconductor package of claim 13, wherein the lower structure is an interposer.

17. The semiconductor package of claim 13, wherein the lower structure is another semiconductor chip different from the semiconductor chip.

18. A semiconductor package comprising:

a lower structure; and

a plurality of semiconductor chips provided on the lower structure,

wherein the plurality of semiconductor chips comprises a first semiconductor chip and a second semiconductor chip in direct contact with each other,

wherein the first semiconductor chip has a first upper side and a first lower side that opposes the first upper side,

wherein the second semiconductor chip has a second upper side and a second lower side that opposes the second upper side,

wherein the first semiconductor chip comprises an upper insulating layer and an upper pad that are provided at the first upper side of the first semiconductor chip,

wherein the second semiconductor chip comprises a lower insulating layer and a lower pad that are provided at the second lower side of the second semiconductor chip,

wherein the lower insulating layer and the upper insulating layer are in contact with and coupled to each other,

wherein the lower pad and the upper pad are in contact with and coupled to each other, and

wherein the second lower side of the second semiconductor chip is narrower than the second upper side of the second semiconductor chip.

19. The semiconductor package of claim 18, wherein the second lower side of the second semiconductor chip is narrower than the first upper side of the first semiconductor chip.

20. The semiconductor package of claim 19, wherein the first lower side of the first semiconductor chip and the second lower side of the second semiconductor chip have a same width, and

wherein the first upper side of the first semiconductor chip and the second upper side of the second semiconductor chip have a same width.