INTEGRATED CIRCUIT INCLUDING SUPERVIA AND METHOD OF MAKING

• US 20200135640A1
• Filed: 08/02/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: SIO, Kam-Tou, TZENG, Jiann-Tyng, LIN, Wei-Cheng
• Granted Patent: US 11,270,936 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses

Abstract

An integrated circuit includes a substrate and a first conductive line extending in a first direction parallel to a top surface of the substrate, wherein the first conductive line is a first distance from the top surface of the substrate. The integrated circuit further includes a second conductive line extending in a second direction parallel to the top surface of the substrate, wherein the second conductive line is a second distance from the top surface of the substrate, and the second distance is greater than the first distance. The integrated circuit further includes a third conductive line extending in the first direction, wherein the second conductive line is a third distance from the top surface of the substrate, and the third distance is greater than the second distance. The integrated circuit further includes a supervia directly connected to the first conductive line and the third conductive line.

Claims

1. An integrated circuit comprising:

a substrate;

a first conductive line extending in a first direction parallel to a top surface of the substrate, wherein the first conductive line is a first distance from the top surface of the substrate;

a second conductive line extending in a second direction parallel to the top surface of the substrate, wherein the second conductive line is a second distance from the top surface of the substrate, and the second distance is greater than the first distance;

a third conductive line extending in the first direction, wherein the second conductive line is a third distance from the top surface of the substrate, and the third distance is greater than the second distance; and

a supervia directly connected to the first conductive line and the third conductive line.

2. The integrated circuit of claim 1, wherein the supervia has a uniform tapered profile.

3. The integrated circuit of claim 1, wherein the supervia has a varied tapered profile.

4. The integrated circuit of claim 1, further comprising a fourth conductive line extending in the first direction, wherein the fourth conductive line is the first distance from the top surface of the substrate.

5. The integrated circuit of claim 4, further comprising a second supervia directly connected to the fourth conductive line and the second conductive line.

6. The integrated circuit of claim 1, wherein the first direction is perpendicular to the second direction.

7. The integrated circuit of claim 1, further comprising:

a first dielectric layer surrounding the second conductive line; and

a second dielectric layer surrounding the third conductive line.

8. The integrated circuit of claim 7, wherein the supervia extends through the first dielectric layer and the second dielectric layer.

9. The integrated circuit of claim 1, wherein the supervia comprises:

a first section directly connected to the first conductive line, wherein a sidewall of the first section extends at a first angle with respect to the top surface of the substrate; and

a second section directly connected to the third conductive line, wherein a sidewall of the second section extends at a second angle with respect to the top surface of the substrate, and the first angle is different from the second angle.

10. The integrated circuit of claim 9, wherein a thickness of the first section is greater than a thickness of the second section.

11. An integrated circuit comprising:

a first dielectric layer;

a first conductive line in the first dielectric layer;

a second dielectric layer over the first dielectric layer;

a third dielectric layer over the second dielectric layer;

a second conductive line in the third dielectric layer; and

a supervia directly connected to the first conductive line and the second conductive line, wherein the supervia has a varied tapered profile.

12. The integrated circuit of claim 11, wherein the supervia extends partially through the third dielectric layer.

13. The integrated circuit of claim 11, further comprising a third conductive line in the second dielectric layer.

14. The integrated circuit of claim 11, wherein the supervia comprises:

a first section directly connected to the first conductive line, wherein the first section is in the second dielectric layer; and

a second section directly connected to the second conductive line, wherein the second section is in the third dielectric layer.

15. The integrated circuit of claim 14, wherein a thickness of the first section is greater than a thickness of the second section.

16. A method comprising:

depositing a first dielectric layer over a first conductive line;

forming a first opening in the first dielectric layer;

filling the first opening with a first conductive material to define a second conductive line;

depositing a second dielectric layer over the first dielectric layer;

forming a second opening in the second dielectric layer;

filling the second opening with a second conductive material to define a third conductive line;

forming a supervia opening in the first dielectric layer and the second dielectric layer; and

filling the supervia opening with a third conductive material to define a supervia, wherein the supervia directly connects to the first conductive line and the third conductive line.

17. The method of claim 16, wherein forming the supervia opening comprises forming a portion of the supervia opening simultaneously with forming the first opening.

18. The method of claim 16, wherein forming the supervia opening comprises forming a portion of the supervia opening simultaneously with forming the second opening.

19. The method of claim 16, wherein filling the supervia opening comprises filling a portion of the supervia opening simultaneously with filling the first opening.

20. The method of claim 16, wherein filling the supervia opening comprises filling a portion of the supervia opening simultaneously with filling the second opening.