POWER DISTRIBUTION NETWORKS FOR MONOLITHIC THREE-DIMENSIONAL SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES

• US 20200135645A1
• Filed: 10/25/2019
• Published: 04/30/2020
• Est. Priority Date: 10/26/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Rubin, Joshua M., Hook, Terence B.
• Granted Patent: US 10,910,312 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Devices and methods are provided for fabricating monolithic three-dimensional semiconductor integrated circuit devices which include power distribution networks that are implemented with power distribution planes disposed below a stack of device tiers, in between device tiers, and/or above the device tiers to distribute positive and negative power supply voltage to field-effect transistor devices of the device tiers.

Claims

1. A method, comprising:

forming a backside layer comprising a first power distribution plane;

forming a first device tier over the backside layer, wherein the first device tier comprises an integrated circuit comprising field-effect transistor devices;

forming at least one interlayer via which vertically connects a source/drain region of at least one field-effect transistor device of the first device tier to the first power distribution plane;

forming a second device tier over the first device tier, wherein the second device tier comprises an integrated circuit comprising field-effect transistor devices;

forming a back-end-of-line layer over the second device tier, and

forming an interconnect structure which extends from the back-end-of-line layer through the second and first second device tiers in contact with the first power distribution plane to connect at least one of positive power supply voltage and negative power supply voltage to the first power distribution plane.

2. The method of claim 1, wherein the first power distribution plane comprises at least one metallic plate, wherein the at least one interlayer via provides a direct vertical connection from the source/drain region of the at least one field-effect transistor device of the first device tier to the at least one metallic plate of the first power distribution plane.

3. The method of claim 1, wherein the first power distribution plane comprises a plurality of parallel wires, wherein the at least one interlayer via provides a direct vertical connection from the source/drain region of the at least one field-effect transistor device of the first device tier to at least one of the plurality of parallel wires.

4. The method of claim 1, further comprising forming a second power distribution plane in the back-end-of-line layer, wherein the second power distribution plane is configured to distribute at least one of positive power supply voltage and negative power supply voltage to the field-effect transistor devices of the second device tier.

5. The method of claim 4, wherein the first power distribution plane is configured to distribute negative power supply voltage to the field-effect transistor devices of the first device tier, and wherein the second power distribution plane is configured to distribute positive power supply voltage to the field-effect transistor devices of the second device tier.

6. The method of claim 4, wherein the first power distribution plane is configured to distribute positive power supply voltage to the field-effect transistor devices of the first device tier, and wherein the second power distribution plane is configured to distribute negative power supply voltage to the field-effect transistor devices of the second device tier.

7. The method of claim 4, wherein the second power distribution plane comprises a metallic plate and a plurality of contact pads which are isolated from the metallic plate by insulating spacers surrounding the contact pads.

8. The method of claim 7, wherein the vertical interconnect structure which extends from the back-end-of-line layer through the first and second device tiers, and in contact with the first power distribution plane, is formed, in part, by at least one of the contact pads of the second power distribution plane.

9. The method of claim 4, wherein the second power distribution plane comprises a plurality of parallel wires.

10. The method of claim 1, further comprising forming an inter-tier power distribution plane over the first device tier, before forming the second device tier.

11. The method of claim 10, wherein the inter-tier power distribution plane comprises a metallic plate and a plurality of contact pads which are isolated from the metallic plate by insulating spacers surrounding the contact pads.

12. A method comprising:

forming a first device tier, wherein the first device tier comprises an integrated circuit comprising field-effect transistor devices;

forming an inter-tier power distribution plane over the first device tier;

forming a second device tier over the inter-tier power distribution plane and the first device tier, wherein the second device tier comprises an integrated circuit comprising field-effect transistor devices;

forming at least one interlayer via which vertically connects a source/drain region of at least one field-effect transistor device of the second device tier to the inter-tier power distribution plane;

forming a back-end-of-line layer over the second device tier; and

forming a first vertical interconnect structure which extends from the back-end-of-line layer through the second device tier in contact with the inter-tier power distribution plane to connect at least one of positive power supply voltage and negative power supply voltage to the inter-tier power distribution plane.

13. The method of claim 12, wherein the inter-tier power distribution plane comprises at least one metallic plate and a plurality of contact pads which are isolated from the metallic plate by insulating spacers surrounding the contact pads, wherein the at least one interlayer via provides a direct vertical connection from the source/drain region of the at least one field-effect transistor device of the second device tier to the at least one metallic plate of the inter-tier power distribution plane.

14. The method of claim 12, wherein the inter-tier power distribution plane comprises a plurality of parallel wires, wherein the at least one interlayer via provides a direct vertical connection from the source/drain region of the at least one field-effect transistor device of the second device tier to at least one of the plurality of parallel wires.

15. The method of claim 12, further comprising:

forming a backside power distribution plane;

bonding the first device tier to the backside power distribution plane; and

forming a second vertical interconnect structure which extends from the back-end-of-line layer through the second and first device tiers in contact with the backside power distribution plane to connect at least one of positive power supply voltage and negative power supply voltage to the backside power distribution plane.

16. The method of claim 15, wherein the backside power distribution plane is configured to distribute negative power supply voltage to the field-effect transistor devices of the first device tier, and wherein the inter-tier power distribution plane is configured to distribute positive power supply voltage to the field-effect transistor devices of the second device tier.

17. The method of claim 15, wherein the backside power distribution plane is configured to distribute positive power supply voltage to the field-effect transistor devices of the first device tier, and wherein the inter-tier power distribution plane is configured to distribute negative power supply voltage to the field-effect transistor devices of the second device tier.

18. A method for fabricating a semiconductor device, comprising:

forming a backside layer comprising a first power distribution plane;

forming a first device tier over the backside layer, wherein the first device tier comprises an integrated circuit comprising field-effect transistor devices;

forming at least one interlayer via which vertically connects a source/drain region of at least one field-effect transistor device of the first device tier to the first power distribution plane;

forming a second device tier over the first device tier, wherein the second device tier comprises an integrated circuit comprising field-effect transistor devices;

forming a back-end-of-line layer over second device tier; and

forming a second power distribution plane which comprises a metallic plate and a plurality of contact pads which are isolated from the metallic plate by insulating spacers surrounding the contact pads, wherein the second power distribution plane is one of disposed (i) within the back-end-of-line layer and (ii) between the first and second device tiers.

19. The method of claim 18, wherein forming the second power distribution plane comprises:

forming a pattern of sacrificial mandrels, wherein the sacrificial mandrels define the contact pads of the second power distribution plane;

forming insulating spacers surrounding the sacrificial mandrels;

performing an etch process to etch the sacrificial mandrels selective to the insulating spacers and remove the sacrificial mandrels; and

depositing a layer of metallic material to fill regions within the insulating spacers to form the contact pads and to fill the region outside the insulating spaces to form the metallic plate.

20. The method of claim 19, further comprising forming an interconnect structure which extends from the back-end-of-line layer through the first and second device tiers, and in contact with the first power distribution plane, wherein the interconnect structure comprises at least one isolated contact pad of the second power distribution plane to vertically route the interconnect structure through the second power distribution plane.