SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

• US 20200135647A1
• Filed: 01/01/2020
• Published: 04/30/2020
• Est. Priority Date: 05/05/2016
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Hsu, Chih-Kai, Hung, Yu-Hsiang, Cheng, Wei-Chi, Fu, Ssu-I, Jenq, Jyh-Shyang
• Granted Patent: US 10,978,398 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/28525 the conductive layers comprising semiconducting material H01L21/28518, H01L21/28537 take precedence
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76819 Smoothing of the dielectric planarisation of insulating materials per se H01L21/31051
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76855 After-treatment introducing at least one additional element into the layer
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming an epitaxial layer adjacent to the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a first contact hole in the ILD layer adjacent to the gate structure; and forming a cap layer in the recess, in which a top surface of the cap layer is even with or lower than a top surface of the substrate.

Claims

1. A method for fabricating semiconductor device, comprising:

providing a substrate;

forming a gate structure on the substrate;

forming an epitaxial layer adjacent to the gate structure;

forming an interlayer dielectric (ILD) layer on the gate structure;

forming a first contact hole in the ILD layer adjacent to the gate structure; and

forming a cap layer in the recess, wherein a top surface of the cap layer is even with or lower than a top surface of the substrate.

2. The method of claim 1, further comprising:

forming a metal layer on the cap layer to fill the first contact hole; and

planarizing the metal layer to form a first contact plug.

3. The method of claim 2, further comprising forming a silicide between the first contact plug and the cap layer.

4. The method of claim 1, further comprising:

forming a second contact hole in the ILD layer to expose the gate structure;

forming a metal layer in the second contact hole; and

planarizing the metal layer to form a second contact plug.

5. The method of claim 1, further comprising:

forming a contact etch stop layer (CESL) on the gate structure and the substrate;

forming the ILD layer; and

removing part of the ILD layer and part of the CESL to form the first contact hole.

6. The method of claim 1, wherein the cap layer and the epitaxial layer comprise same material.

7. The method of claim 6, wherein a doping concentration of the cap layer is higher than a doping concentration of the epitaxial layer.

8. The method of claim 1, further comprising forming a buffer layer before forming the epitaxial layer.

9. The method of claim 8, wherein the buffer layer, the epitaxial layer, and the cap layer comprise same material.

10. The method of claim 1, wherein the top surface of the cap layer comprises a reverse V-shaped profile.

11. The method of claim 1, wherein the top surface of the cap layer comprises a V-shaped profile.