SEMICONDUCTOR PACKAGE HAVING NONSPHERICAL FILLER PARTICLES

• US 20200135648A1
• Filed: 06/30/2017
• Published: 04/30/2020
• Est. Priority Date: 06/30/2017
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: KANDANUR, Sashi, UNRUH, JR., David Allen, PIETAMBARAM, Srinivas V.
• Granted Patent: US 11,127,682 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/481 Insulating layers on insulating parts, with or without metallisation
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/145 Organic substrates, e.g. plastic
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

Semiconductor packages having nonspherical filler particles are described. In an embodiment, a semiconductor package includes a package substrate having a dielectric layer over an electrical interconnect. The dielectric layer includes nonspherical filler particles in a resin matrix. The nonspherical filler particles have an aspect ratio greater than one.

Claims

1. A semiconductor package, comprising:

a package substrate including a dielectric layer over an electrical interconnect layer, wherein the dielectric layer includes a plurality of nonspherical filler particles in a resin matrix; and

a semiconductor die mounted on the package substrate.

2. The semiconductor package of claim 1, wherein the resin matrix includes an organic resin material, and wherein the plurality of nonspherical filler particles include an inorganic material.

3. The semiconductor package of claim 2, wherein each of the plurality of nonspherical filler particles has a respective aspect ratio greater than 1.

4. The semiconductor package of claim 3, wherein the respective aspect ratios are greater than 1.5.

5. The semiconductor package of claim 3, wherein the plurality of nonspherical filler particles are cylindrical.

6. The semiconductor package of claim 3, wherein the plurality of nonspherical filler particles are ellipsoidal.

7. The semiconductor package of claim 2, wherein the dielectric layer includes a top surface, wherein the plurality of nonspherical filler particles have respective exposed surfaces at the top surface, and wherein the respective exposed surfaces are coplanar with an upper surface of the resin matrix at the top surface.

8. The semiconductor package of claim 7, wherein the respective exposed surfaces have different areal shapes.

9. The semiconductor package of claim 7, wherein each of the plurality of nonspherical filler particles includes a respective longitudinal axis at a respective angle to the respective exposed surface, wherein the respective exposed surface has a respective maximum dimension, and wherein the respective angle relates reciprocally to the respective maximum dimension.

10. The semiconductor package of claim 9, wherein each of the plurality of nonspherical filler particles includes a functionalized outer surface.

11. A semiconductor package assembly, comprising:

a printed circuit board; and

a semiconductor package mounted on the printed circuit board, the semiconductor package including

a package substrate including a dielectric layer over an electrical interconnect layer, wherein the dielectric layer includes a plurality of nonspherical filler particles in a resin matrix, and

a semiconductor die mounted on the package substrate, wherein the semiconductor die is electrically connected to the electrical interconnect layer.

12. The semiconductor package assembly of claim 11, wherein each of the plurality of nonspherical filler particles has a respective aspect ratio greater than 1.

13. The semiconductor package assembly of claim 12, wherein the respective aspect ratios are greater than 1.5.

14. The semiconductor package assembly of claim 12, wherein the plurality of nonspherical filler particles are one or more of cylindrical or ellipsoidal.

15. The semiconductor package assembly of claim 11, wherein the dielectric layer includes a top surface, wherein the plurality of nonspherical filler particles have respective exposed surfaces at the top surface, and wherein the respective exposed surfaces are coplanar with an upper surface of the resin matrix at the top surface.

16. A method, comprising:

forming an electrical interconnect layer over a core layer of a package substrate;

forming a dielectric layer over the electrical interconnect layer, wherein the dielectric layer includes a plurality of nonspherical filler particles in a resin matrix; and

removing a portion of the dielectric layer to form a top surface, wherein the top surface includes respective exposed surfaces of the plurality of nonspherical filler particles and an upper surface of the resin matrix.

17. The method of claim 16, wherein the respective exposed surfaces of the plurality of nonspherical filler particles are coplanar with the upper surface of the resin matrix.

18. The method of claim 17, wherein the electrical interconnect layer includes an electrical via having an exposed via surface at the top surface, and wherein the exposed via surface is coplanar with the respective exposed surfaces of the plurality of nonspherical filler particles and the upper surface of the resin matrix.

19. The method of claim 16, wherein forming the dielectric layer includes:

functionalizing an outer surface of the plurality of nonspherical filler particles; and

dispersing the plurality of nonspherical filler particles in the resin matrix.

20. The method of claim 16 further comprising mounting a semiconductor die on the package substrate, wherein the semiconductor die is electrically connected to the electrical interconnect layer.