PACKAGE STRUCTURE, SEMICONDUCTOR PACAKGE AND METHOD OF FABRICATING THE SAME

• US 20200135649A1
• Filed: 12/27/2019
• Published: 04/30/2020
• Est. Priority Date: 07/15/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Jung-Hua, Kao, Chin-Fu
• Granted Patent: US 11,004,797 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/76876 for deposition from the gas phase, e.g. CVD
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/68331 of passive members, e.g. die mounting substrate
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto when forming bonding pads H01L24/03; when forming bump connectors H01L24/11; when forming layer connectors H01L24/27
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms

Abstract

A package structure including a first semiconductor die, a second semiconductor die, a molding compound, an interconnect structure, first conductive features, through insulator vias, an insulating encapsulant and a redistribution layer is provided. The molding compound is encapsulating the first semiconductor die and the second semiconductor die. The interconnect structure is disposed on the molding compound and electrically connecting the first semiconductor die to the second semiconductor die. The first conductive features are electrically connected to the first semiconductor die and the second semiconductor die, wherein each of the first conductive features has a recessed portion. The through insulator vias are disposed on the recessed portion of the first conductive features and electrically connected to the first and second semiconductor die. The insulating encapsulant is encapsulating the interconnect structure and the through insulator vias. The redistribution layer is disposed on the insulating encapsulant and over the interconnect structure.

Claims

1. A structure, comprising:

a plurality of semiconductor dies;

a molding compound encapsulating the plurality of semiconductor dies;

a plurality of first conductive features disposed on and electrically connected to the plurality of semiconductor dies, wherein the plurality of first conductive features has a recessed portion;

a plurality of through insulator vias disposed on the recessed portion of the plurality of first conductive features and electrically connected to the plurality of semiconductor dies;

an interconnect structure disposed on the plurality of semiconductor dies and overlapping with two adjacent semiconductor dies, wherein top surfaces of the plurality of through insulator vias are leveled with a surface of the interconnect structure; and

an insulating encapsulant disposed on the molding compound and encapsulating the interconnect structure and the plurality of through insulator vias, and separating the interconnection structure from the plurality of through insulator vias.

2. The structure according to claim 1, further comprising a plurality of second conductive features disposed on and electrically connected to the plurality of semiconductor dies, wherein the interconnect structure is electrically connected to the plurality of semiconductor die through the plurality of second conductive features.

3. The structure according to claim 2, wherein a width of the plurality of second conductive features is smaller than a width of the plurality of first conductive features.

4. The structure according to claim 1, further comprising a plurality of seed layers disposed in between the recessed portion of the plurality of first conductive features and the plurality of through insulator vias.

5. The structure according to claim 1, further comprising a redistribution layer disposed on the insulating encapsulant and over the interconnect structure, wherein the redistribution layer is electrically connected to the plurality of through insulator vias.

6. The structure according to claim 1, wherein the interconnect structure comprises:

a silicon interconnect;

a plurality of conductive vias disposed on the silicon interconnect; and

a plurality of conductive bumps disposed on the plurality of conductive vias.

7. The structure according to claim 6, further comprising an underfill structure disposed over the plurality of semiconductor die and covering the plurality of conductive vias and the plurality of conductive bumps.

8. A semiconductor package, comprising:

a first semiconductor die comprising a plurality of conductive vias;

a dielectric layer disposed on the first semiconductor die and having first openings that reveal a portion of the plurality of conductive vias, and second openings that reveal another portion of the plurality of conductive vias;

a plurality of first conductive features disposed in the first openings of the dielectric layer to be electrically connected to the plurality of conductive vias, wherein each of the first conductive features comprises flank portions and a recessed portion joining the flank portions;

a plurality of second conductive features disposed in the second openings of the dielectric layer to be electrically connected to the plurality of conductive vias;

a plurality of through insulator vias disposed on the recessed portion of the plurality of first conductive features and electrically connected to the first semiconductor die; and

an interconnect structure disposed on the plurality of second conductive features and electrically connected to the first semiconductor die.

9. The semiconductor package according to claim 8, wherein a level of a top surface of the flank portions is higher than a level of a top surface of the recessed portions in the first conductive features.

10. The semiconductor package according to claim 8, wherein a top surface of the flank portions of the first conductive features is levelled with a top surface of the second conductive features.

11. The semiconductor package according to claim 8, further comprising:

a second semiconductor die disposed adjacent to the first semiconductor die and having a plurality of conductive vias, wherein the plurality of first conductive features and the plurality of second conductive features are further electrically connected to the plurality of conductive vias of the second semiconductor die.

12. The semiconductor package according to claim 11, wherein the interconnect structure is electrically connected to the first semiconductor die and the second semiconductor die through the plurality of first conductive features.

13. The semiconductor package according to claim 8, further comprising:

a molding compound encapsulating the first semiconductor die; and

an insulating encapsulant encapsulating the plurality of through insulator vias and the interconnect structure, wherein the dielectric layer is disposed in between the molding compound and the insulating encapsulant.

14. The semiconductor package according to claim 13, further comprising a redistribution layer disposed on the insulating encapsulant and over the interconnect structure, wherein the redistribution layer is electrically connected to the first semiconductor die through the plurality of through insulator vias.

15. A method of fabricating a semiconductor package, comprising:

disposing a first semiconductor die having a plurality of conductive vias on a carrier;

forming a dielectric layer on the first semiconductor die and defining first openings and second openings in the dielectric layer, wherein the first openings reveal a portion of the plurality of conductive vias, and the second openings reveal another portion of the plurality of conductive vias;

forming a plurality of first conductive features in the first openings of the dielectric layer to be electrically connected to the plurality of conductive vias, wherein the plurality of first conductive features comprises flank portions and a recessed portion joining the flank portions;

forming a plurality of second conductive features in the second openings of the dielectric layer to be electrically connected to the plurality of conductive vias;

forming a plurality of through insulator vias on the recessed portion of the plurality of first conductive features, wherein the plurality of through insulator vias is electrically connected to the first semiconductor die;

disposing an interconnect structure on the plurality of second conductive feature, wherein the interconnect structure is electrically connected to the first semiconductor die; and

debonding the carrier.

16. The method of fabricating the semiconductor package according to claim 15, wherein a width of the first openings is greater than a width of the second openings.

17. The method of fabricating the semiconductor package according to claim 15, wherein the plurality of through insulator vias is formed by the following steps:

forming a seed layer on the dielectric layer and over the first conductive features and the second conductive features;

providing a photoresist pattern on the seed layer covering the plurality of second conductive features and the flank portions of the plurality of first conductive features, wherein the photoresist pattern has openings exposing portions of the seed layer located above the recessed portions;

forming a metallic material on the exposed portions of the seed layer to form the plurality of through insulator vias; and

removing the photoresist pattern and portions of the seed layer exposed by the through insulator vias.

18. The method of fabricating the semiconductor package according to claim 15, further comprising:

disposing a second semiconductor die on the carrier adjacent to the first semiconductor die, wherein the plurality of first conductive features and the plurality of second conductive features are further electrically connected to the second semiconductor die.

19. The method of fabricating the semiconductor package according to claim 18, wherein the interconnect structure is electrically connected to the first semiconductor die and the second semiconductor die through the plurality of first conductive features.

20. The method of fabricating the semiconductor package according to claim 15, further comprising:

forming a molding compound on the carrier to encapsulate the first semiconductor die; and

forming an insulating encapsulant on the dielectric layer to encapsulate the plurality of through insulator vias and the interconnect structure, wherein the dielectric layer is located in between the molding compound and the insulating encapsulant.