PACKAGE STRUCTURE, SEMICONDUCTOR PACAKGE AND METHOD OF FABRICATING THE SAME
First Claim
1. A structure, comprising:
- a plurality of semiconductor dies;
a molding compound encapsulating the plurality of semiconductor dies;
a plurality of first conductive features disposed on and electrically connected to the plurality of semiconductor dies, wherein the plurality of first conductive features has a recessed portion;
a plurality of through insulator vias disposed on the recessed portion of the plurality of first conductive features and electrically connected to the plurality of semiconductor dies;
an interconnect structure disposed on the plurality of semiconductor dies and overlapping with two adjacent semiconductor dies, wherein top surfaces of the plurality of through insulator vias are leveled with a surface of the interconnect structure; and
an insulating encapsulant disposed on the molding compound and encapsulating the interconnect structure and the plurality of through insulator vias, and separating the interconnection structure from the plurality of through insulator vias.
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Accused Products
Abstract
A package structure including a first semiconductor die, a second semiconductor die, a molding compound, an interconnect structure, first conductive features, through insulator vias, an insulating encapsulant and a redistribution layer is provided. The molding compound is encapsulating the first semiconductor die and the second semiconductor die. The interconnect structure is disposed on the molding compound and electrically connecting the first semiconductor die to the second semiconductor die. The first conductive features are electrically connected to the first semiconductor die and the second semiconductor die, wherein each of the first conductive features has a recessed portion. The through insulator vias are disposed on the recessed portion of the first conductive features and electrically connected to the first and second semiconductor die. The insulating encapsulant is encapsulating the interconnect structure and the through insulator vias. The redistribution layer is disposed on the insulating encapsulant and over the interconnect structure.
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Citations
20 Claims
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1. A structure, comprising:
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a plurality of semiconductor dies; a molding compound encapsulating the plurality of semiconductor dies; a plurality of first conductive features disposed on and electrically connected to the plurality of semiconductor dies, wherein the plurality of first conductive features has a recessed portion; a plurality of through insulator vias disposed on the recessed portion of the plurality of first conductive features and electrically connected to the plurality of semiconductor dies; an interconnect structure disposed on the plurality of semiconductor dies and overlapping with two adjacent semiconductor dies, wherein top surfaces of the plurality of through insulator vias are leveled with a surface of the interconnect structure; and an insulating encapsulant disposed on the molding compound and encapsulating the interconnect structure and the plurality of through insulator vias, and separating the interconnection structure from the plurality of through insulator vias. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor package, comprising:
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a first semiconductor die comprising a plurality of conductive vias; a dielectric layer disposed on the first semiconductor die and having first openings that reveal a portion of the plurality of conductive vias, and second openings that reveal another portion of the plurality of conductive vias; a plurality of first conductive features disposed in the first openings of the dielectric layer to be electrically connected to the plurality of conductive vias, wherein each of the first conductive features comprises flank portions and a recessed portion joining the flank portions; a plurality of second conductive features disposed in the second openings of the dielectric layer to be electrically connected to the plurality of conductive vias; a plurality of through insulator vias disposed on the recessed portion of the plurality of first conductive features and electrically connected to the first semiconductor die; and an interconnect structure disposed on the plurality of second conductive features and electrically connected to the first semiconductor die. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A method of fabricating a semiconductor package, comprising:
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disposing a first semiconductor die having a plurality of conductive vias on a carrier; forming a dielectric layer on the first semiconductor die and defining first openings and second openings in the dielectric layer, wherein the first openings reveal a portion of the plurality of conductive vias, and the second openings reveal another portion of the plurality of conductive vias; forming a plurality of first conductive features in the first openings of the dielectric layer to be electrically connected to the plurality of conductive vias, wherein the plurality of first conductive features comprises flank portions and a recessed portion joining the flank portions; forming a plurality of second conductive features in the second openings of the dielectric layer to be electrically connected to the plurality of conductive vias; forming a plurality of through insulator vias on the recessed portion of the plurality of first conductive features, wherein the plurality of through insulator vias is electrically connected to the first semiconductor die; disposing an interconnect structure on the plurality of second conductive feature, wherein the interconnect structure is electrically connected to the first semiconductor die; and debonding the carrier. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification