PACKAGE STRUCTURE WITH BUMP

• US 20200135651A1
• Filed: 12/23/2019
• Published: 04/30/2020
• Est. Priority Date: 10/03/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: CHIU, Ming-Yen, HUANG, Hsin-Chieh, CHANG, Ching-Fu
• Granted Patent: US 10,879,185 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13026 relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/14135 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A package structure is provided. The package structure includes a redistribution layer and a first integrated circuit chip having a first chip edge and a second integrated circuit chip having a second chip edge over the redistribution layer. The package structure also includes first bumps electrically connected to the first integrated circuit chip through the redistribution layer. In addition, the first bumps overlap the first integrated circuit chip and are arranged along a first chip edge of the first integrated circuit chip. The package structure further includes second bumps electrically connected to the first integrated circuit chip through the redistribution layer without overlapping the first integrated circuit chip and the second integrated circuit chip. In addition, none of the second bumps is arranged between the first chip edge and the second chip edge.

Claims

1. A package structure, comprising:

a redistribution layer;

a first integrated circuit chip having a first chip edge and a second integrated circuit chip having a second chip edge over the redistribution layer;

first bumps electrically connected to the first integrated circuit chip through the redistribution layer, wherein the first bumps overlap the first integrated circuit chip and are arranged along a first chip edge of the first integrated circuit chip in plan view; and

second bumps electrically connected to the first integrated circuit chip through the redistribution layer without overlapping the first integrated circuit chip and the second integrated circuit chip, wherein none of the second bumps is arranged between the first chip edge and the second chip edge in plan view.

2. The package structure as claimed in claim 1, wherein the second bumps partially surround the first chip edge and the second chip edge in plan view.

3. The package structure as claimed in claim 1, wherein a distance between the neighboring first bumps is different from a distance between the neighboring first bumps and second bumps.

4. The package structure as claimed in claim 1, further comprising:

a molding compound surrounding the first integrated circuit chip and the second integrated circuit chip, wherein the molding compound has a first portion sandwiched between the first chip edge and the second chip edge without overlapping the first bumps and the second bumps in a top view.

5. The package structure as claimed in claim 1, further comprising:

first under-bump metallurgy (UBM) elements between the redistribution layer and the first bumps and arranged along the first chip edge; and

second UBM elements between the redistribution layer and the second bumps and arranged along the first chip edge, wherein none of the first and second UBM elements overlaps the first chip edge.

6. The package structure as claimed in claim 1, wherein the second bumps are arranged along a third chip edge of the first integrated circuit chip and a fourth chip edge of the second integrated circuit chip, and the third chip edge of the first integrated circuit chip is substantially aligned with the fourth chip edge of the second integrated circuit chip.

7. The package structure as claimed in claim 1, wherein there is a keep-out zone between the first bumps and the second bumps in top view and a width of the keep-out zone is in a range from about 30 μ

m to about 200 μ

m.

8. A package structure, comprising:

a redistribution layer;

a first integrated circuit chip having a first chip edge and a second integrated circuit chip having a second chip edge over the redistribution layer;

a first bump and a second bump connected to the redistribution layer;

wherein the first bump is directly under the first integrated circuit chip and the second bump are directly under a region between the first chip edge and the second chip edge, and a distance between the second bump and the first chip edge is different from a distance between the first bump and the first chip edge.

9. The package structure as claimed in claim 8, further comprising:

a plurality of the first bumps directly under the first integrated circuit chip; and

a plurality of the second bumps directly under a region between the first chip edge and the second chip edge,

wherein two of the first bumps are spaced apart from each other by a first distance, and a minimum distance between one of the second bumps and the two of the first bumps is greater than the first distance, and the one of the second bumps is directly adjacent to the first chip edge and the second chip edge, and the two of the first bumps and the one of the second bumps are substantially aligned.

10. The package structure as claimed in claim 9, wherein the one of the second bumps is spaced apart from the first chip edge and the second chip edge by different distances in a top view.

11. The package structure as claimed in claim 9,

wherein the second bumps surround the first bumps, and no bump overlaps the first chip edge and the second chip edge.

12. The package structure as claimed in claim 9, further comprising:

a package layer surrounding the first integrated circuit chip and the second integrated circuit chip over the redistribution layer; and

a first conductive feature formed through the package layer,

wherein the first conductive feature overlaps at least one of the second bumps.

13. The package structure as claimed in claim 9,

further comprising:

first under-bump metallurgy (UBM) elements between the redistribution layer and the first bumps; and

second UBM elements between the redistribution layer and the second bumps,

wherein the first UBM elements and the second UBM elements are arranged without overlapping the first chip edge and the second chip edge.

14. A package structure, comprising:

a package layer;

a first chip in the package layer, wherein the first chip has a first chip edge;

a second chip in the package layer, wherein the second chip has a second chip edge;

first bumps under the first chip;

second bumps under the second chip; and

third bumps under the package layer without overlapping the first chip and the second chip,

wherein a distance between the first chip edge and the second chip edge is smaller than a distance between two of the neighboring first bumps.

15. The package structure as claimed in claim 14, wherein the third bumps partially surround the first chip edge and the second chip edge in a top view.

16. The package structure as claimed in claim 14, wherein a first group of the third bumps are aligned along a first side of the first chip edge and a first side of the second chip edge, and the first side of the first chip edge is substantially aligned with the first side of the second chip edge.

17. The package structure as claimed in claim 16, wherein a second side of the first chip edge faces a second side of the second chip edge, and a first portion of the package layer is sandwiched between the second side of the first chip edge and the second side of the second chip edge, and no bump is disposed under the first portion of the package layer.

18. The package structure as claimed in claim 14, wherein the distance between the first chip edge and the second chip edge is smaller than a distance between one of the first bumps and one of the second bumps neighboring with each other.

19. The package structure as claimed in claim 14, wherein no bump overlaps the first chip edge or the second chip edge.

20. The package structure as claimed in claim 16, wherein the first bumps and the second bumps are surrounded by the third bumps.