CHIP PACKAGE WITH FAN-OUT STRUCTURE

• US 20200135652A1
• Filed: 12/23/2019
• Published: 04/30/2020
• Est. Priority Date: 10/13/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: CHEN, Shing-Chao, LIN, Chih-Wei, CHIANG, Tsung-Hsien, CHENG, Ming-Da, HSIEH, Ching-Hua
• Granted Patent: US 11,404,381 B2
• Time in Patent Office: Days
• CPC Class Codes: B29C 45/14639 for obtaining an insulating effect, e.g. for electrical components
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/566 Release layers for moulds, e.g. release layers, layers against residue during moulding
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto when forming bonding pads H01L24/03; when forming bump connectors H01L24/11; when forming layer connectors H01L24/27
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1041 : Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5383 : Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5386 : Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/18 : High density interconnect [HDI] connectors; Manufacturing methods related thereto interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/1203 : Rectifying Diode
• CPC Class Codes: H01L 2924/1304 : Transistor
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1431 : Logic devices

Abstract

A chip package is provided. The chip package includes a semiconductor die and a protection layer surrounding the semiconductor die. The chip package also includes a first dielectric layer over the semiconductor die and the protection layer. The first dielectric layer has an upper surface with cutting scratches. The chip package further includes a conductive layer over the first dielectric layer. In addition, the chip package includes a second dielectric layer over the conductive layer and filling some of the cutting scratches. Bottoms of the cutting scratches are positioned at height levels that are lower than a topmost surface of the first dielectric layer and higher than a topmost surface of the semiconductor die.

Claims

1. A chip package, comprising:

a semiconductor die;

a protection layer surrounding the semiconductor die;

a first dielectric layer over the semiconductor die and the protection layer, wherein the first dielectric layer has an upper surface with cutting scratches;

a conductive layer over the first dielectric layer; and

a second dielectric layer over the conductive layer and filling some of the cutting scratches, wherein bottoms of the cutting scratches are positioned at height levels that are lower than a topmost surface of the first dielectric layer and higher than a topmost surface of the semiconductor die.

2. The chip package as claimed in claim 1, further comprising a conductive structure in the protection layer and separated from the semiconductor die by a portion of the protection layer, wherein the protection layer has a recessed portion between the semiconductor die and the conductive structure.

3. The chip package as claimed in claim 2, wherein the first dielectric layer fills the recessed portion of the protection layer.

4. The chip package as claimed in claim 2, wherein a top surface of the conductive structure is between the topmost surface of the first dielectric layer and a bottommost surface of the first dielectric layer.

5. The chip package as claimed in claim 1, wherein an interface between the second dielectric layer and the first dielectric layer has an undulate morphology.

6. The chip package as claimed in claim 1, wherein widths of the cutting scratches are substantially the same.

7. The chip package as claimed in claim 1, wherein each of the cutting scratches has a width in a range from about 20 μ

m to about 60 μ

m, and each of the cutting scratches has a depth in a range from about 0.05 μ

m to about 0.1 μ

m.

8. The chip package as claimed in claim 1, wherein the conductive layer fills some of the scratches that are not filled with the second dielectric layer.

9. The chip package as claimed in claim 1, wherein intervals between the cutting scratches are substantially the same.

10. The chip package as claimed in claim 1, wherein the second dielectric layer is in direct contact with sidewalls of some of the cutting scratches.

11. A chip package, comprising:

a semiconductor die;

a protection layer surrounding the semiconductor die;

a first dielectric layer over the semiconductor die and the protection layer;

a conductive layer over the first dielectric layer; and

a second dielectric layer over the first dielectric layer and the conductive layer, wherein the second dielectric layer has a plurality of protruding portions extending into the first dielectric layer, and bottoms of the protruding portions are positioned at height levels that are lower than a topmost surface of the first dielectric layer and higher than a topmost surface of the semiconductor die.

12. The chip package as claimed in claim 11, wherein widths of the protruding portions of the second dielectric layer are substantially the same.

13. The chip package as claimed in claim 11, wherein each of the protruding portions of the second dielectric layer has a width in a range from about 20 μ

m to about 60 μ

m, and each of the protruding portions of the conductive layer has a height in a range from about 0.05 μ

m to about 0.1 μ

m.

14. The chip package as claimed in claim 11, wherein the conductive layer has a plurality of second protruding portions extending into the first dielectric layer.

15. The chip package as claimed in claim 14, wherein a width of each of the protruding portions of the second dielectric layer is substantially equal to a width of each of the second protruding portions of the conductive layer.

16. A chip package, comprising:

a semiconductor die;

a protection layer surrounding the semiconductor die;

a first dielectric layer over the semiconductor die and the protection layer; and

a conductive layer over the first dielectric layer; and

a second dielectric layer over the first dielectric layer and the conductive layer, wherein an interface between the second dielectric layer and the first dielectric layer has an undulate morphology, and bottoms of the interface with the undulated morphology are positioned at height levels that are lower than a topmost surface of the first dielectric layer and higher than a topmost surface of the semiconductor die.

17. The chip package as claimed in claim 16, wherein an interface between the conductive layer and the first dielectric layer has a second undulate morphology.

18. The chip package as claimed in claim 17, wherein the undulate morphology and the second undulate morphology are substantially the same.

19. The chip package as claimed in claim 16, further comprising a conductive structure in the protection layer and separated from the semiconductor die by a portion of the protection layer, wherein the protection layer has a recessed portion between the semiconductor die and the conductive structure.

20. The chip package as claimed in claim 16, further comprising a conductive structure in the protection layer and separated from the semiconductor die by a portion of the protection layer, wherein a top surface of the conductive structure is between the topmost surface of the first dielectric layer and a bottommost surface of the first dielectric layer.