Graphene Layer for Reduced Contact Resistance

• US 20200135655A1
• Filed: 09/04/2019
• Published: 04/30/2020
• Est. Priority Date: 10/25/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yang, Shin-Yi, Lee, Ming-Han, Shue, Shau-Lin
• Granted Patent: US 11,094,631 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76864 Thermal treatment
• CPC Class Codes: H01L 21/76867 characterized by methods of formation other than PVD, CVD or deposition from a liquids PVD H01L21/2855; CVD H01L21/28556; deposition from liquids H01L21/288
• CPC Class Codes: H01L 21/76871 Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
• CPC Class Codes: H01L 21/76876 for deposition from the gas phase, e.g. CVD
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53276 containing carbon, e.g. fullerenes superconducting fullerenes H10N60/853

Abstract

A method includes forming a trench within a dielectric layer, the trench comprising an interconnect portion and a via portion, the via portion exposing an underlying conductive feature. The method further includes depositing a seed layer within the trench, depositing a carbon layer on the seed layer, performing a carbon dissolution process to cause a graphene layer to form between the seed layer and the underlying conductive feature, and filling a remainder of the trench with a conductive material.

Claims

1. A method comprising:

forming a trench within a dielectric layer, the trench comprising an interconnect portion and a via portion, the via portion exposing an underlying conductive feature;

depositing a seed layer within the trench;

depositing a carbon layer on the seed layer;

performing a carbon dissolution process to cause a graphene layer to form between the seed layer and the underlying conductive feature; and

filling a remainder of the trench with a conductive material.

2. The method of claim 1, wherein the seed layer is formed in both the interconnect portion and the via portion.

3. The method of claim 1, further comprising, before forming the seed layer, depositing a pre-fill material in the via portion, wherein the seed layer is formed on the pre-fill material in the trench.

4. The method of claim 1, wherein the seed layer comprises one of:

nickel, cobalt, iron or copper.

5. The method of claim 1, wherein a thickness of the seed layer is within a range of about 5-100 Angstroms.

6. The method of claim 1, wherein the carbon layer is deposited via one of:

Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD, Plasma Enhanced Atomic Layer Deposition (PEALD) or Plasma Enhanced Chemical Vapor Deposition (PECVD).

7. The method of claim 1, wherein the carbon layer has a thickness within a range of about 5-100 Angstroms.

8. The method of claim 1, wherein the carbon dissolution process comprises an annealing process applied at a temperature range of about 200-1200 degrees.

9. The method of claim 8, wherein the annealing process performed with a pressure range of about 0.25 torr-30 atm.

10. The method of claim 1, further comprising, after the carbon dissolution process, removing the carbon layer.

11. The method of claim 10, wherein the carbon layer is removed using one of wet-etching or dry-etching.

12. A method comprising:

forming a trench within a dielectric layer, the trench exposing an underlying conductive feature;

depositing a seed layer within the trench;

depositing a carbon layer on the seed layer;

performing a carbon dissolution process to case a graphene layer to form between the seed layer and the underlying conductive feature; and

removing the carbon layer.

13. The method of claim 12, wherein the trench comprises an upper portion and a lower portion.

14. The method of claim 13, further comprising, depositing the seed layer in both the upper portion and the lower portion.

15. The method of claim 13, further comprising, depositing a pre-fill layer in the lower portion.

16. The method of claim 15, wherein depositing the seed layer comprises depositing the seed layer in the upper portion and on the pre-fill layer.

17. The method of claim 12, wherein the seed layer is one of:

cobalt, iron, copper, and nickel.

18. A semiconductor structure comprising:

a conductive feature embedded within an interlayer dielectric layer (ILD);

an interconnect feature embedded within the ILD;

a via electrically connecting the conductive feature to the interconnect feature;

a graphene layer positioned between the via and the conductive feature, the graphene layer in direct contact with the conductive feature; and

a seed layer positioned between the graphene layer and the via.

19. The semiconductor structure of claim 18, wherein the graphene layer has a thickness within a range of about 1-10 atoms.

20. The semiconductor structure of claim 18, wherein the seed layer comprises one of:

nickel, iron, copper, and cobalt.