PACKAGE STRUCTURE

• US 20200135661A1
• Filed: 12/31/2019
• Published: 04/30/2020
• Est. Priority Date: 12/13/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: LEE, Hsiao-Wen, LIU, Hsien-Wen, JENG, Shin-Puu
• Granted Patent: US 11,056,445 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/0223 formation by oxidation, e.g. oxidation of the substrate
• CPC Class Codes: H01L 21/3043 Making grooves, e.g. cutting
• CPC Class Codes: H01L 21/48 Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68318 Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/118 Post-treatment of the bump connector
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/214 : Connecting portions
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3135 : Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/3178 : Coating or filling in grooves made in the semiconductor body
• CPC Class Codes: H01L 23/3192 : Multilayer coating
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5383 : Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5386 : Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/18 : High density interconnect [HDI] connectors; Manufacturing methods related thereto interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect

Abstract

Package structures are provided. A package structure includes an adhesive layer and a semiconductor substrate over the adhesive layer. The package structure also includes a connector over the semiconductor substrate. The package structure further includes a first buffer layer surrounding the connector. In addition, the package structure includes an encapsulation layer surrounding the first buffer layer. The first buffer layer is sandwiched between the encapsulation layer and the semiconductor substrate, and a sidewall of the encapsulation layer is in direct contact with a sidewall of the first buffer layer and a sidewall of the adhesive layer. The package structure also includes a redistribution layer over the first buffer layer and the encapsulation layer.

Claims

1. A package structure, comprising:

an adhesive layer;

a semiconductor substrate over the adhesive layer;

a connector over the semiconductor substrate;

a first buffer layer surrounding the connector;

an encapsulation layer surrounding the first buffer layer, wherein the first buffer layer is sandwiched between the encapsulation layer and the semiconductor substrate, and a sidewall of the encapsulation layer is in direct contact with a sidewall of the first buffer layer and a sidewall of the adhesive layer; and

a redistribution layer over the first buffer layer and the encapsulation layer.

2. The package structure as claimed in claim 1, wherein a portion of the adhesive layer extends outwardly from a sidewall of the semiconductor substrate.

3. The package structure as claimed in claim 2, wherein the first buffer layer overlies the portion of the adhesive layer extending outwardly from the sidewall of the semiconductor substrate.

4. The package structure as claimed in claim 1, wherein an interface between the adhesive layer and the encapsulation layer is substantially coplanar with an interface between the first buffer layer and the encapsulation layer.

5. The package structure as claimed in claim 1, further comprising a second buffer layer covering a sidewall of the semiconductor substrate, wherein the first buffer layer surrounds the second buffer layer.

6. The package structure as claimed in claim 5, wherein the second buffer layer extends between the first buffer layer and the connector over a top surface of the semiconductor substrate.

7. The package structure as claimed in claim 5, wherein the second buffer layer extends from the sidewall of the semiconductor substrate to a bottom surface of the semiconductor substrate.

8. The package structure as claimed in claim 1, further comprising a second buffer layer over a top surface of the semiconductor substrate, wherein the connector is embedded in the second buffer layer and separated from the first buffer layer by the second buffer layer.

9. A package structure, comprising:

a semiconductor substrate over an adhesive layer;

a first buffer layer over the adhesive layer, wherein the first buffer layer overlies a sidewall of the semiconductor substrate;

a connector over the semiconductor substrate;

an encapsulation layer surrounding the adhesive layer, the first buffer layer and the connector, wherein the encapsulation layer covers a sidewall of the first buffer layer and a sidewall of the adhesive layer; and

a passivation layer over the connector and the encapsulation layer.

10. The package structure as claimed in claim 9, wherein the first buffer layer extends from the sidewall of the semiconductor substrate to the connector.

11. The package structure as claimed in claim 9, further comprising a second buffer layer over the adhesive layer, wherein the first buffer layer is attached to the sidewall of the semiconductor substrate through the second buffer layer.

12. The package structure as claimed in claim 9, further comprising a second buffer layer between the adhesive layer and the semiconductor substrate, wherein the second buffer extends along the sidewall of the semiconductor substrate and is covered by the first buffer layer.

13. The package structure as claimed in claim 9, further comprising a second buffer layer over the adhesive layer, wherein the adhesive layer is in direct contact with the first buffer layer and the second buffer layer, and the semiconductor substrate is separated from the adhesive layer by the second buffer layer.

14. The package structure as claimed in claim 9, wherein the sidewall of the adhesive layer is substantially aligned with the sidewall of the first buffer layer.

15. A package structure, comprising:

a semiconductor substrate over an adhesive layer;

a connector over the semiconductor substrate;

a first buffer layer covering a top surface of the semiconductor substrate and a sidewall of the connector;

a second buffer layer covering a sidewall of the semiconductor substrate and a sidewall of the first buffer layer, wherein an interface between the first buffer layer and the second buffer layer is overlapped with the adhesive layer; and

an encapsulation layer surrounding the second buffer layer.

16. The package structure as claimed in claim 15, wherein the interface is substantially coplanar with the sidewall of the semiconductor substrate.

17. The package structure as claimed in claim 15, wherein top surfaces of the first buffer layer, the second buffer layer and the connector are substantially level with one another.

18. The package structure as claimed in claim 15, wherein a bottom surface of the semiconductor substrate is substantially level with a bottom surface of the second buffer layer.

19. The package structure as claimed in claim 15, wherein a sidewall of the adhesive layer is substantially aligned with a sidewall of the second buffer layer.

20. The package structure as claimed in claim 15, wherein a sidewall of the encapsulation layer is in direct contact with a sidewall of the second buffer layer and a sidewall of the adhesive layer.