CUSTOMISATION OF AN INTEGRATED CIRCUIT DURING THE REALISATION THEREOF

• US 20200135663A1
• Filed: 10/29/2019
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: Commissariat a L'Energie Atomique (AES Corporation)
• Original Assignee: Commissariat A L'Energie Atomique Aux Energies Alternatives
• Inventors: LANDIS, Stefan, Teyssedre, Hubert
• Granted Patent: US 10,886,239 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 21/73 by creating or determining hardware identification, e.g. serial numbers
• CPC Class Codes: H01L 21/0332 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76847 the layer being positioned within the main fill metal
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/57 Protection from inspection, reverse engineering or tampering
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 9/3278 using physically unclonable functions [PUF]

Abstract

A method for securing an integrated circuit during the realization thereof, including the following steps: delimiting the integrated circuit into a first zone referred to as standard zone and into a second zone referred to as security zone, forming of a set of vias in the security zone, and introducing of a layer loaded with contaminant particles configured to randomly obstruct a portion of the vias, thus forming a random interconnection structure in the security zone, the random interconnection structure creating a physical unclonable function.

Claims

1. A method for securing an integrated circuit during realisation thereof, said method comprising the following steps:

delimiting of said integrated circuit into a first zone referred to as standard zone and into a second zone referred to as security zone,

introducing of a layer of resin loaded with contaminant particles configured to randomly obstruct during a step of etching of the security zone a portion of the vias provided in said security zone thus forming a random set of vias, and

metalizing of said random set of vias of the security zone in order to form a random interconnection structure that defines a physical unclonable function.

2. The method according to claim 1, wherein the contaminant particles are nanoparticles formed from a material of the dielectric or metallic type selected from the following materials:

silicon, silicon dioxide SiO2, silicon, metal TiN.

3. The method according to claim 1, wherein the contaminant particles have a diameter that is substantially greater than or equal to that of the vias.

4. The method according to claim 1, wherein the contaminant particles have a concentration between about 0.1% to 20% by mass selected according to the size of the particles.

5. The method according to claim 1, wherein the securing of the integrated circuit is integrated on the realisation of the first vias and further comprises the following steps:

realising a first level of conductive patterns on the surface of said standard and security zones,

depositing on the surface of the first level of conductive patterns of a first multilayer comprising a metal diffusion barrier as well as an etching mask,

depositing on the surface of the first multilayer of a second multilayer of photosensitive resin comprising said layers loaded with contaminant particles,

optical lithography in the security zone for insulating the vias provided in this security zone, with the standard zone remaining protected by the second multilayer,

transferring of the vias of the security zone non-obstructed or obstructed by contaminant particles in the etching mask,

cleaning of the surface of the standard and security zones in order to remove the second multilayer.

6. The method according to claim 5, wherein the second multilayer comprises a first layer of etching mask of the carbon-enriched organic layer type SOC, a second layer of etching mask of the silicon-enriched organic layer type SiARC and a third layer of photosensitive resin, the contaminant particles being comprised in said first layer of etching mask SOC.

7. The method according to claim 6, further comprising the following steps:

depositing on the surface of the standard and security zones of at least one third multilayer of photosensitive resin,

optical lithography in the standard zone for insulating the vias provided in the standard zone,

transferring of the vias of the standard zone in the etching mask,

re-cleaning of the surface of the standard and security zones in order to remove the third multilayer of photosensitive resin,

transferring in the metal diffusion barrier layer and filling by a metal of the vias in the standard and security zones, and

realising of a second level of conductive patterns on the surface of the standard and security zones.

8. The method according to claim 1, wherein an application of a voltage greater than a reading voltage in order to break down fragile partial vias.

9. The method according to claim 1, wherein the random interconnection structure models a random electrical continuity that can be queried by a challenge-response authentication protocol, said random interconnection structure being formed between at least two corresponding levels of conductive patterns, with a portion of the conductive patterns being configured to receive a challenge, while another portion of the conductive patterns is configured to supply the response to said challenge.

10. The method according to claim 1, wherein the realisation of a plurality of random interconnection structures and of a plurality of corresponding levels of conductive patterns.

11. The method according to claim 1, wherein the securing of the integrated circuit is realised at the manufacturing of logic circuits.

12. A secure integrated circuit, comprising:

a first zone referred to as standard zone comprising at least two levels of conductive tracks connected via metal interconnections to electronic components,

a second zone referred to as security zone comprising a random interconnection structure formed between at least two levels of corresponding conductive patterns adapted to test the electrical continuity of said random interconnection structure and thus defining a physical unclonable function.