SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME
First Claim
1. A semiconductor package comprising:
- a first integrated circuit die, the first integrated circuit die comprising;
a first substrate comprising an active device;
an interconnect structure overlying the first substrate and comprising multiple metal layers with vias connecting the multiple metal layers, the interconnect structure being electrically coupled to the active device;
a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure comprising multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, the inner metal structure being spaced apart from the outer metal structure; and
a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over a top surface of the outer metal structure of the seal ring structure, the outermost edge of the polymer layer being laterally between sidewalls of the outer metal structure of the seal ring structure.
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Accused Products
Abstract
A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.
4 Citations
20 Claims
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1. A semiconductor package comprising:
a first integrated circuit die, the first integrated circuit die comprising; a first substrate comprising an active device; an interconnect structure overlying the first substrate and comprising multiple metal layers with vias connecting the multiple metal layers, the interconnect structure being electrically coupled to the active device; a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure comprising multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, the inner metal structure being spaced apart from the outer metal structure; and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over a top surface of the outer metal structure of the seal ring structure, the outermost edge of the polymer layer being laterally between sidewalls of the outer metal structure of the seal ring structure. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A semiconductor package comprising:
a first die, the first die comprising; a first semiconductor substrate having an active device in a first surface of the first semiconductor substrate; a plurality of dielectric layers over the first surface of the first semiconductor substrate; a plurality of metal layers and vias in the plurality of dielectric layers, the plurality of metal layers and vias comprising; a first portion of the plurality of metal layers and vias electrically coupled to the active device; and a second portion of the plurality of metal layers and vias along a periphery of the first semiconductor substrate, the second portion of the plurality of metal layers and vias surrounding the first portion of the plurality of metal layers and vias; a first passivation layer over the plurality of dielectric layers and the plurality of metal layers and vias; a first redistribution layer over the first passivation layer and extending through the first passivation layer to physically contact the first portion of the plurality of metal layers and vias; a second redistribution layer over the first passivation layer and extending through the first passivation layer to physically contact the second portion of the plurality of metal layers and vias; and a polymer layer over the first redistribution layer and the second redistribution layer, the polymer layer having an outermost edge that is over and laterally within the bounds of a top surface of the second redistribution layer. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. A method comprising:
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forming a plurality of active devices in a wafer, the wafer comprising a plurality of die regions, each of the die regions having at least one active device; forming an interconnect structure over the wafer, the interconnect structure comprising a plurality of metal layers and vias in a plurality of dielectric layers, the plurality of metal layers and vias in each of the plurality of die regions comprising; a first portion of the plurality of metal layers and vias electrically coupled to one of the plurality of active devices; and a second portion of the plurality of metal layers and vias along a periphery of the respective die region; forming a first passivation layer over the interconnect structure; forming redistribution layers over the first passivation layer, each of the plurality of die regions comprising a first redistribution layer and a second redistribution layer, the first redistribution layer extending through the first passivation layer to physically contact the respective first portion of the plurality of metal layers and vias, the second redistribution layer extending through the first passivation layer to physically contact the respective second portion of the plurality of metal layers and vias; and forming a polymer layer over the redistribution layers, the polymer layer having an outermost edge that is over and laterally within the bounds of top surfaces of the second redistribution layers. - View Dependent Claims (19, 20)
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Specification