PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

• US 20200135670A1
• Filed: 11/20/2018
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsu, Sen-Kuei, Pan, Hsin-Yu
• Granted Patent: US 10,840,197 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2223/6627 Waveguides, e.g. microstrip line, strip line, coplanar line
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02373 Layout of the redistribution layers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/22 of a plurality of HDI interconnects
• CPC Class Codes: H01L 2224/26175 Flow barriers
• CPC Class Codes: H01L 2224/2731 in liquid form
• CPC Class Codes: H01L 2224/27312 : Continuous flow, e.g. using a microsyringe, a pump, a nozzle or extrusion
• CPC Class Codes: H01L 2224/2732 : Screen printing, i.e. using a stencil
• CPC Class Codes: H01L 2224/29294 : with a principal constituent of the material being a liquid not provided for in groups H01L2224/292 - H01L2224/29291
• CPC Class Codes: H01L 2224/293 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/29339 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/32227 : the layer connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/83192 : wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/9202 : Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/92144 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5226 : Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/66 : High-frequency adaptations
• CPC Class Codes: H01L 24/09 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01Q 1/2283 : mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
• CPC Class Codes: H01Q 1/523 : between antennas of an array
• CPC Class Codes: H01Q 1/526 : Electromagnetic shields
• CPC Class Codes: H01Q 21/065 : Patch antenna array

Abstract

A package structure includes a first redistribution circuit structure, a second redistribution circuit structure, a semiconductor die, a waveguide structure, and an antenna. The semiconductor die is sandwiched between and electrically coupled to the first redistribution circuit structure and the second redistribution circuit structure. The waveguide structure is located aside and electrically coupled to the semiconductor die, wherein the waveguide structure includes a part of the first redistribution circuit structure, a part of the second redistribution circuit structure and a plurality of first through vias each connecting to the part of the first redistribution circuit structure and the part of the second redistribution circuit structure. The antenna is located on the semiconductor die, wherein the second redistribution circuit structure is sandwiched between the antenna and the semiconductor die, and the antenna is electrically communicated with the semiconductor die through the waveguide structure.

Claims

1. A package structure, comprising:

a first redistribution circuit structure and a second redistribution circuit structure;

at least one semiconductor die, sandwiched between and electrically coupled to the first redistribution circuit structure and the second redistribution circuit structure;

at least one waveguide structure, located aside and electrically coupled to the at east one semiconductor die, wherein the at least one waveguide structure comprises;

a part of the first redistribution circuit structure;

a part of the second redistribution circuit structure; and

a plurality of first through vias, each connecting to the part of the first redistribution circuit structure and the part of the second redistribution circuit structure, wherein a channel is located in the at least one waveguide structure and enclosed by the part of the first redistribution circuit structure, the part of the second redistribution circuit structure and the plurality of first through vias; and

an antenna, located on the at least one semiconductor die, wherein the second redistribution circuit structure is sandwiched between the antenna and the at least one semiconductor die, and the antenna is electrically communicated with the at least one semiconductor die through the at least one waveguide structure.

2. The package structure of claim 1, wherein a signal transmitting from the at least one semiconductor die to the antenna or transmitting from the antenna to to the at least one semiconductor die is in an electromagnetic wave form propagating inside the channel.

3. The package structure of claim 2, wherein a shape of the channel comprising a shape in form of a linear line or a shape in form of a curved line having one or more than one bending portions.

4. The package structure of claim 1, further comprising:

an insulating encapsulation, encapsulating the at least one waveguide structure and the at least one semiconductor die, wherein the insulating encapsulation is located between the first redistribution structure and the second redistribution structure;

an encapsulant, sandwiched between the antenna and the second redistribution circuit structure; and

conductive elements, located on and connected to the first redistribution circuit structure, wherein the first redistribution circuit structure is sandwiched between the conductive elements and the insulating encapsulation.

5. The package structure of claim 4, further comprising:

a plurality of second through vias, encapsulating in the insulating encapsulation and electrically connected to the at least one semiconductor die, wherein positioning locations of the plurality of second through vias are aside of positioning locations of the plurality of first through vias and a positioning location of the at least one semiconductor die on a vertical projection on the encapsulant.

6. The package structure of claim 1, further comprising:

a first isolation structure, located on the second redistribution circuit structure, wherein the first isolation structure is spacing apart from the antenna.

7. The package structure of claim 6, wherein the first isolation structure comprises:

a plurality of third through vias, penetrating the encapsulant and a portion of the second redistribution circuit structure and electrically connected to the second redistribution circuit structure; and

a first connecting structure, located on the encapsulant and in contact with the plurality of third through vias, wherein the plurality of third through vias are electrically connected to one another through the first connecting structure.

8. The package structure of claim 1, further comprising:

second isolation structures, located on the second redistribution circuit structure, wherein the second isolation structures are spacing apart from the antenna.

9. The package structure of claim 8, wherein each of the second isolation structures comprises:

a fourth through via, penetrating the encapsulant and a portion of the second redistribution circuit structure and electrically connected to the second redistribution circuit structure; and

a second connecting structure, located on the encapsulant and in contact with the fourth through via.

10. A package structure, comprising:

a first redistribution circuit structure and a second redistribution circuit structure;

at least one semiconductor die, sandwiched between and electrically coupled to the first redistribution circuit structure and the second redistribution circuit structure;

at least one waveguide structure, located aside and electrically coupled to the at least one semiconductor die;

antennas, located on the at least one semiconductor die, wherein the second redistribution circuit structure is sandwiched between the antennas and the at least one semiconductor die, and the antennas are electrically communicated with the at least one semiconductor die through the at least one waveguide structure; and

at least one first isolation structure, located on and electrically coupled to the second redistribution circuit structure, wherein the at least one first isolation structure is located between and separated apart from the antennas.

11. The package structure of claim 10, further comprising an encapsulant sandwiched between the antennas and the second redistribution circuit structure, wherein the at least one first isolation structure comprises:

a plurality of first through vias, penetrating the encapsulant and a portion of the second redistribution circuit structure and electrically connected to the second redistribution circuit structure; and

a first connecting structure, located on the encapsulant and in contact with the plurality of first through vias, wherein the plurality of first through vias are electrically connected to one another through the first connecting structure.

12. The package structure of claim 11, further comprising second isolation structures located on the second redistribution circuit structure, wherein the second isolation structures are spacing apart from the antennas, wherein each of the second isolation structures comprises:

a second through via, penetrating the encapsulant and a portion of the second redistribution circuit structure and electrically connected to the second redistribution circuit structure; and

a second connecting structure, located on the encapsulant and in contact with the second through via.

13. The package structure of claim 10, further comprising an encapsulant sandwiched between the antennas and the second redistribution circuit structure, wherein the at least one first isolation structure comprises a plurality of first isolation structure each comprising:

a second through via, penetrating the encapsulant and a portion of the second redistribution circuit structure and electrically connected to the second redistribution circuit structure; and

a second connecting structure, located on the encapsulant and in contact with the second through via.

14. The package structure of claim 13, further comprising a third isolation structure located on the second redistribution circuit structure, wherein the third isolation structure is spacing apart from the antennas, wherein the third isolation structure comprises:

a plurality of third through vias, penetrating the encapsulant and a portion of the second redistribution circuit structure and electrically connected to the second redistribution circuit structure; and

a third connecting structure, located on the encapsulant and in contact with all the plurality of third through vias, wherein the plurality of third through vias are electrically connected to one another through the third connecting structure.

15. The package structure of claim 10, further comprising:

an insulating encapsulation, encapsulating the at least one waveguide structure and the at least one semiconductor die, wherein the insulating encapsulation is located between the first redistribution structure and the second redistribution structure;

conductive elements, located on and connected to the first redistribution circuit structure, wherein the first redistribution circuit structure is sandwiched between the conductive elements and the insulating encapsulation; and

a plurality of fourth through vias, encapsulating in the insulating encapsulation and electrically connected to the at least one semiconductor die, wherein positioning locations of the plurality of fourth through vias are aside of a positioning location of the at least one waveguide structure and a positioning location of the at least one semiconductor die on a vertical projection on the insulating encapsulation.

16. The package structure of claim 10, wherein a signal transmitting from the at least one semiconductor die to the antennas or transmitting from the antennas to the at least one semiconductor die is in an electromagnetic wave form propagating inside a channel located in the at least one waveguide structure.

17. The package structure of claim 16, wherein a shape of the channel comprising a shape in form of a linear line or a shape in form of a curved line having one or more than one bending portions.

18. A method of manufacturing a package structure, comprising:

forming a first redistribution circuit structure;

disposing at least one semiconductor die and forming a plurality of through vias on the first redistribution circuit structure, the plurality of through vias being located aside the at least one semiconductor die, and the at least one semiconductor die and the plurality of through vias being electrically connected to the first redistribution circuit structure;

encapsulating the at least one semiconductor die and the plurality of through vias in an insulating encapsulation;

forming a second redistribution circuit structure on the insulating encapsulation, the at least one semiconductor die and the plurality of through vias being electrically connected to the second redistribution circuit structure so to form at least one waveguide structure aside of the at least one semiconductor die and having a channel located in the at least one waveguide structure, wherein the channel is enclosed by a part of the first redistribution circuit structure, a part of the second redistribution circuit structure and the plurality of first through vias; and

disposing an antenna on the second redistribution circuit structure, wherein the second redistribution circuit structure is located between the antenna and the at least one semiconductor die, wherein the at least one semiconductor die is electrically communicated to the antenna through at least one waveguide structure.

19. The method of claim 18, further comprising:

forming an encapsulant prior to disposing the antenna on the second redistribution circuit structure, the encapsulant being sandwiched between the antenna and the second redistribution circuit structure; and

forming a first isolation structure and a plurality of second isolation structures after disposing the antenna on the second redistribution circuit structure, the first isolation structure and the plurality of second isolation structures being separating from the antenna,

wherein the first isolation structure comprises;

a plurality of first through vias, penetrating the encapsulant and a portion of the second redistribution circuit structure and electrically connected to the second redistribution circuit structure; and

a first connecting structure, located on the encapsulant and in contact with all the plurality of first through vias, wherein the plurality of first through vias are electrically connected to one another through the first connecting structure,

wherein each of the second isolation structures comprises;

one second through via, penetrating the encapsulant and a portion of the second redistribution circuit structure and electrically connected to the second redistribution circuit structure; and

a second connecting structure, located on the encapsulant and in contact with the second through via.

20. The method of claim 18, further comprising:

forming a plurality of third through vias prior to encapsulating the at least one semiconductor die and the plurality of through vias in the insulating encapsulation, the plurality of third through vias being connecting to the first redistribution circuit structure and located aside the at least one semiconductor die, wherein the plurality of the third through vias are encapsulated in and penetrating through the insulating encapsulation so as to connect to the second redistribution circuit structure, and wherein the plurality of the third through vias are electrically connected to the at least one semiconductor die.