SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20200135675A1
• Filed: 10/25/2018
• Published: 04/30/2020
• Est. Priority Date: 10/25/2018
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: LU, Wen-Long
• Granted Patent: US 10,700,029 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13164 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/13169 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48229 the bond pad protruding from the surface of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/81192 wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/85439 : Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/85444 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/85447 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/85455 : Nickel (Ni) as principal constituent
• CPC Class Codes: H01L 2224/85464 : Palladium (Pd) as principal constituent
• CPC Class Codes: H01L 2224/85469 : Platinum (Pt) as principal constituent
• CPC Class Codes: H01L 2224/85484 : Tungsten (W) as principal constituent
• CPC Class Codes: H01L 2224/92125 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 23/13 : characterised by the shape
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/53238 : Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/066 : Phenolic resin
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/07025 : Polyimide
• CPC Class Codes: H01L 2924/0715 : Polysiloxane
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/35121 : Peeling or delaminating

Abstract

A semiconductor package device includes a first conductive structure, a second conductive structure and a dielectric layer. The first conductive structure has a tapered portion. The second conductive structure surrounds the tapered portion of the first conductive structure and is in direct contact with a side wall of the tapered portion of the first conductive structure. The dielectric layer surrounds the tapered portion of the first conductive structure and is in direct contact with the side wall of the tapered portion of the first conductive structure.

Claims

1. A semiconductor packaging device, comprising:

a first conductive structure having a tapered portion;

a second conductive structure surrounding the tapered portion of the first conductive structure and being in direct contact with a side wall of the tapered portion of the first conductive structure; and

a dielectric layer surrounding the tapered portion of the first conductive structure and being in direct contact with the side wall of the tapered portion of the first conductive structure,

wherein the second conductive structure comprises a first conductive portion and a second conductive portion, the first conductive portion being surrounded by the dielectric layer and the second conductive portion protruding from the first conductive portion and beyond a first surface of the dielectric layer, and

wherein the first conductive structure comprises a barrier layer extended from the tapered portion to a second surface of the dielectric layer opposite to the first surface of the dielectric layer, and the barrier layer contacts the dielectric layer.

6. The semiconductor packaging device of claim 1, wherein a gap is located between the barrier layer and the dielectric layer, and the second conductive structure fills the gap.

7. The semiconductor packaging device of claim 1, wherein the barrier layer comprises a Ti layer.

8. The semiconductor packaging device of claim 1, wherein the first conductive structure comprises a Cu layer, the Cu layer defining a receiving surface to contact with the second conductive structure.

9. The semiconductor packaging device of claim 1, wherein a material of the second conductive structure comprises Sn.

10. The semiconductor packaging device of claim 1, further comprising a semiconductor chip arranged above a first surface of the dielectric layer and electrically connected to the first conductive structure.

2. (canceled)

3. The semiconductor packaging device of claim 2, wherein the first conductive portion of the second conductive structure and the second conductive portion of the second conductive structure forms a neck.

4. The semiconductor packaging device of claim 2, wherein a first surface of the dielectric layer and the first conductive portion of the second conductive structure define an angle θ

, and the angle θ

is in the range from 70°

to 85°

.

5. (canceled)

11. A semiconductor packaging device, comprising:

a first conductive structure having a first portion;

a second conductive structure having a first portion engaged with the first portion of the first conductive structure; and

a dielectric layer having a first portion engaged with the first portion of the second conductive structure,

wherein the second conductive structure comprises a second portion protruding from the first portion of the second conductive structure and beyond a first surface of the dielectric layer, and wherein the first portion of the second conductive structure and the second portion of the second conductive structure form a neck, and

wherein the first conductive structure comprises a barrier layer extended from the first portion to a second surface of the dielectric layer opposite to the first surface of the dielectric layer, and the barrier layer contacts the dielectric layer,

wherein the second conductive structure comprises a second portion protruding from the first portion of the second conductive structure and beyond a first surface of the dielectric layer, and wherein the first portion of the second conductive structure and the second portion of the second conductive structure form a neck, and

wherein the first conductive structure comprises a barrier layer extended from the first portion to a second surface of the dielectric layer opposite to the first surface of the dielectric layer, and the barrier layer contacts the dielectric layer.

14. The semiconductor packaging device of claim 11, wherein the first conductive structure comprises a Cu layer, the Cu layer defining a receiving surface to contact with the second conductive structure, and wherein the Cu layer contacts with the barrier layer.

15. The semiconductor packaging device of claim 11, wherein a gap is located between the barrier layer and the dielectric layer, and the second conductive structure fills the gap.

16. The semiconductor packaging device of claim 11, further comprising a barrier overhang surrounding the neck.

17. The semiconductor packaging device of claim 11, further comprising a soldering overhang surrounding the neck.

18. The semiconductor packaging device of claim 11, wherein a first surface of the dielectric layer and the first portion of the second conductive structure define an angle θ

, and the angle θ

is in the range from 70°

to 85°

.

19. The semiconductor packaging device of claim 11, wherein the first conductive structure has a tapered portion.

12-13. -13. (canceled)

20. A method of forming the semiconductor packaging device, comprising:

providing a metal plate;

forming a dielectric layer on the metal plate, and patterning the dielectric layer to form one or more openings to expose a portion of the metal plate, the one or more openings having tapered sidewalls and arc-shaped corners at a bottom of the one or more openings;

forming dome-shaped metal films at the bottom of the one or more openings;

forming a first conductive structure extending from the bottom of the one or more openings to a top surface of the dielectric layer;

removing the metal plate and the dome-shaped metal films to define a receiving space; and

forming a second conductive structure at the receiving space.