SIDEWALL SPACER TO REDUCE BOND PAD NECKING AND/OR REDISTRIBUTION LAYER NECKING

• US 20200135676A1
• Filed: 05/20/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Kalnitsky, Alexander, Thei, Kong-Beng
• Granted Patent: US 10,879,200 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 2224/02126 Collar structures
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02373 Layout of the redistribution layers
• CPC Class Codes: H01L 2224/02375 Top view
• CPC Class Codes: H01L 2224/02381 Side view
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03452 Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/03462 Electroplating
• CPC Class Codes: H01L 2224/03464 Electroless plating
• CPC Class Codes: H01L 2224/0362 Photolithography
• CPC Class Codes: H01L 2224/03622 using masks
• CPC Class Codes: H01L 2224/0381 Cleaning, e.g. oxide removal step, desmearing
• CPC Class Codes: H01L 2224/03831 involving a chemical process, e.g. etching the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05624 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/1145 : Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/11452 : Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/11462 : Electroplating
• CPC Class Codes: H01L 2224/11464 : Electroless plating
• CPC Class Codes: H01L 2224/11849 : Reflowing
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/45147 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 23/3157 : Partial encapsulation or coating mask layer used as insulation layer H01L21/31
• CPC Class Codes: H01L 23/3171 : the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/3192 : Multilayer coating
• CPC Class Codes: H01L 23/5226 : Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5283 : Cross-sectional geometry
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys

Abstract

In some embodiments, an integrated chip (IC) is provided. The IC includes a metallization structure disposed over a semiconductor substrate, where the metallization structure includes an interconnect structure disposed in an interlayer dielectric (ILD) structure. A passivation layer is disposed over the metallization structure, where an upper surface of the interconnect structure is at least partially disposed between opposite inner sidewalls of the passivation layer. A sidewall spacer is disposed along the opposite inner sidewalls of the passivation layer, where the sidewall spacer has rounded sidewalls. A conductive structure is disposed on the passivation layer, the rounded sidewalls of the sidewall spacer, and the upper surface of the interconnect structure.

Claims

1. An integrated chip (IC), comprising:

a semiconductor substrate;

a metallization structure disposed over the semiconductor substrate, the metallization structure comprising an interconnect structure disposed in an interlayer dielectric (ILD) structure;

a passivation layer disposed over the metallization structure, wherein an upper surface of the interconnect structure is at least partially disposed between opposite inner sidewalls of the passivation layer;

a sidewall spacer disposed along the opposite inner sidewalls of the passivation layer, the sidewall spacer having rounded sidewalls; and

a conductive structure disposed on the passivation layer, the rounded sidewalls of the sidewall spacer, and the upper surface of the interconnect structure, wherein the conductive structure is a bond pad and/or a redistribution layer (RDL).

2. The IC of claim 1, wherein the rounded sidewalls of the sidewall spacer face one another.

3. The IC of claim 1, wherein the opposite inner sidewalls of the passivation layer are substantially vertical.

4. The IC of claim 1, wherein a first upper surface of the conductive structure is disposed between the opposite inner sidewalls of the passivation layer and beneath an upper surface of the passivation layer.

5. The IC of claim 4, wherein the conductive structure comprises a sidewall that is rounded and extends from the first upper surface of the conductive structure to a second upper surface of the conductive structure, and wherein the second upper surface of the conductive structure is disposed over the upper surface of the passivation layer and extends laterally beyond one of the opposite inner sidewalls of the passivation layer.

6. The IC of claim 1, further comprising:

an etch stop layer disposed between the passivation layer and the metallization structure, wherein the conductive structure is disposed on opposite inner sidewalls of the etch stop layer.

7. The IC of claim 6, wherein:

the etch stop layer comprises a first dielectric material; and

the passivation layer comprise a second dielectric material different than the first dielectric material.

8. The IC of claim 7, wherein the opposite inner sidewalls of the passivation layer are spaced further apart than the opposite inner sidewalls of the etch stop layer.

9. The IC of claim 8, wherein the opposite inner sidewalls of the etch stop layer are rounded.

10. The IC of claim 9, wherein the rounded opposite inner sidewalls of the etch stop layer and the rounded sidewalls of the sidewall spacer define common rounded sidewalls, respectively.

11. The IC of claim 10, wherein the etch stop layer contacts the sidewall spacer, the passivation layer, the interconnect structure, and the ILD structure.

12. An integrated chip (IC), comprising:

a semiconductor substrate;

a metallization structure disposed over the semiconductor substrate, the metallization structure comprising an interconnect structure disposed in an interlayer dielectric (ILD) structure;

an etch stop layer disposed on the metallization structure, wherein the interconnect structure comprise an uppermost conductive element that is at least partially disposed between opposite inner sidewalls of the etch stop layer;

a passivation layer disposed on the etch stop layer, the passivation layer comprising opposite inner sidewalls that extend from an upper surface of the etch stop layer to an upper surface of the passivation layer;

a sidewall spacer disposed on the etch stop layer and along the opposite inner sidewalls of the passivation layer, wherein the sidewall spacer has rounded sidewalls that face one another; and

a conductive structure disposed on the uppermost conductive element, the opposite inner sidewalls of the etch stop layer, the rounded sidewalls of the sidewall spacer, and the upper surface of the passivation layer.

13. The IC of claim 12, wherein:

the interconnect structure comprise a first conductive material; and

the conductive structure comprises a second conductive material different than the first conductive material.

14. The IC of claim 12, wherein:

a thickness of the sidewall spacer is at least about 40 percent of a height of the passivation layer.

15. The IC of claim 12, further comprising:

a semiconductor device disposed on the semiconductor substrate, wherein the interconnect structure electrically couples the semiconductor device to the conductive structure; and

an input/output (I/O) structure disposed on the conductive structure, wherein the I/O structure is configured to electrically couple the conductive structure to external circuitry.

16. The IC of claim 12, wherein the uppermost conductive element comprises:

opposite inner sidewalls that extend from a first upper surface of the uppermost conductive element to a second upper surface of the uppermost conductive element, wherein the conductive structure is disposed on the opposite inner sidewalls of the uppermost conductive element.

17. The IC of claim 16, wherein the rounded sidewalls of the sidewall spacer, opposite inner sidewalls of the etch stop layer, and the opposite inner sidewalls of the uppermost conductive element define opposite common sidewalls, respectively.

18. A method for forming an integrated chip (IC), the method comprising:

forming a metallization structure over a semiconductor substrate and a semiconductor device on the semiconductor substrate, the metallization structure comprising an interconnect structure disposed in an interlayer dielectric (ILD) structure;

forming an etch stop layer over the metallization structure;

forming a dielectric layer on the etch stop layer;

removing a part of the dielectric layer to form a passivation layer, wherein opposite inner sidewalls of the passivation layer define a first opening;

forming a sidewall spacer on the etch stop layer and along the opposite inner sidewalls of the passivation layer, wherein the sidewall spacer is formed with rounded sidewalls;

removing a part of the etch stop layer to form a second opening that exposes the interconnect structure; and

forming a bond pad or redistribution layer contacting the rounded sidewalls, an upper surface of the passivation layer, and the interconnect structure.

19. The method of claim 18, wherein forming the bond pad comprises:

forming a conductive layer on the passivation layer and lining the second opening;

forming a masking layer on the conductive layer;

with the masking layer disposed on the conductive layer, etching the conductive layer to form the bond pad; and

exposing the masking layer to a stripping agent to remove the masking layer from the bond pad.

20. The method of claim 19, wherein:

the second opening is defined by opposite inner sidewalls of the etch stop layer and the rounded sidewalls of the sidewall spacer; and

the opposite inner sidewalls of the etch stop layer are disposed between the opposite inner sidewalls of the passivation layer.