Protrusion Bump Pads for Bond-on-Trace Processing

• US 20200135678A1
• Filed: 12/27/2019
• Published: 04/30/2020
• Est. Priority Date: 01/06/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liang, Yu-Min, Wu, Jiun Yi
• Granted Patent: US 10,700,034 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16157 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/49866 characterised by the materials materials of the substrates H01L23/14, of the lead-frames H01L23/49579
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/381 : Pitch distance
• CPC Class Codes: H01L 2924/3841 : Solder bridging
• CPC Class Codes: H05K 1/111 : Pads for surface mounting, e.g. lay-out
• CPC Class Codes: H05K 2201/0367 : Metallic bump or raised conductor not used as solder bump solder materials or compositions and methods of application thereof H05K3/3457
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 3/4007 : Surface contacts, e.g. bumps H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3457
• CPC Class Codes: H05K 3/4682 : Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil

Abstract

An embodiment apparatus includes a dielectric layer, a conductive trace in the dielectric layer, and a bump pad. The conductive trace includes a first portion having an exposed top surface, wherein the exposed top surface is recessed from a top surface of the dielectric layer. Furthermore, the bump pad is disposed over and is electrically connected to a second portion of the conductive trace.

Claims

1. A device comprising:

a substrate;

an insulating layer on the substrate;

a conductive line in the insulating layer; and

a conductive pad in the insulating layer and directly over a first region of the conductive line, wherein the conductive pad has a different material composition than the conductive line, wherein a top surface of the conductive pad is not higher than a top surface of the insulating layer, wherein no portions of the insulating layer and no portions of the conductive pad extend directly over a second region of the conductive line.

2. The device of claim 1, wherein the conductive pad comprises nickel or tin, and wherein the conductive line comprises copper.

3. The device of claim 1, wherein the conductive pad is connected to a contact pad through the conductive line, wherein the conductive pad is disposed in the insulating layer, and wherein the device further comprises a conductive pillar extending from the contact pad through the insulating layer.

4. The device of claim 3, wherein the contact pad and the conductive line have a same material composition.

5. The device of claim 3, wherein a top surface of the contact pad is lower than a top surface of the insulating layer.

6. The device of claim 1 further comprising:

an integrated circuit chip; and

a solder region physically coupling the integrated circuit chip to the conductive pad.

7. The device of claim 1, wherein a top surface of the conductive pad is substantially level with the top surface of the insulating layer.

8. The device of claim 1, wherein a top surface of the second region of the conductive line is lower than a top surface of the insulating layer.

9. An apparatus comprising:

a dielectric layer;

a conductive trace in the dielectric layer, wherein the conductive trace comprises a first portion having a first top surface, and wherein a first sidewall of the dielectric layer extends higher than the first top surface of the first portion of the conductive trace; and

a bump pad in the dielectric layer, wherein the bump pad is disposed over and electrically connected to a second portion of the conductive trace, wherein a topmost surface of the bump pad is higher than the first top surface, and wherein the bump pad has a different material composition than the conductive trace.

10. The apparatus of claim 9, wherein the bump pad comprises nickel or tin, and wherein the conductive trace comprises copper.

11. The apparatus of claim 9, wherein the topmost surface of the bump pad is level with a top surface of the dielectric layer.

12. The apparatus of claim 9, wherein the first portion of the conductive trace is free of the bump pad.

13. The apparatus of claim 9, wherein the second portion of the conductive trace extends further into the dielectric layer than the first portion of the conductive trace.

14. The apparatus of claim 9, wherein the first portion of the conductive trace connects the second portion of the conductive trace to a contact pad, wherein the first sidewall of the dielectric layer extends higher than a second top surface of the contact pad.

15. The apparatus of claim 14, wherein the contact pad as a same material composition as the conductive trace.

16. The apparatus of claim 15 further comprising a conductive via extending from a bottom surface of the contact pad to a bottom surface of the dielectric layer.

17. A method, comprising:

separating a substrate from a core of a carrier substrate on which an additional substrate is formed, wherein after separating the substrate from the core, the substrate comprises;

a conductive layer at a top surface of the substrate; and

a plurality of conductive features contacting the conductive layer; and

after separating the substrate from the core, forming a protrusion bump pad over each of a first subset of the conductive features by selectively removing the conductive layer except from over each of the first subset of the conductive features.

18. The method of claim 17, wherein the plurality of conductive features are disposed in a dielectric layer, and wherein the method further comprises recessing a second subset of the conductive features below a top surface of the dielectric layer.

19. The method of claim 18, wherein recessing the second subset of the conductive features is performed using a same etching process as removing the conductive layer except from over each of the first subset of the conductive features.

20. The method of claim 17, further comprising bonding a die to the substrate by disposing a solder region directly on the protrusion bump pad.