SEMICONDUCTOR PACKAGE STRUCTURE WITH CONDUCTIVE LAYER

• US 20200135680A1
• Filed: 12/23/2019
• Published: 04/30/2020
• Est. Priority Date: 05/31/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: CHANG, Jung-Hua, TSAI, Po-Hao, LIN, Jing-Cheng
• Granted Patent: US 11,114,405 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02603 Nanowires
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 2221/68331 of passive members, e.g. die mounting substrate
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto when forming bonding pads H01L24/03; when forming bump connectors H01L24/11; when forming layer connectors H01L24/27
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/215 Material
• CPC Class Codes: H01L 2224/27462 Electroplating
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/3003 Layer connectors having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/3012 Layout
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/821 : Forming a build-up interconnect
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49866 : characterised by the materials materials of the substrates H01L23/14, of the lead-frames H01L23/49579
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/25 : of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/30 : of a plurality of layer connectors
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: Y10S 977/762 : Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less

Abstract

A semiconductor package structure is provided. The semiconductor package structure includes a chip structure. The semiconductor package structure includes a first conductive structure over the chip structure. The first conductive structure is electrically connected to the chip structure. The first conductive structure includes a first transition layer over the chip structure; a first conductive layer on the first transition layer; and a second conductive layer over the first conductive layer. The first conductive layer is substantially made of twinned copper. A first average roughness of a first top surface of the second conductive layer is less than a second average roughness of a second top surface of the first conductive layer

Claims

1. A semiconductor package structure, comprising:

a chip structure; and

a first conductive structure over the chip structure, wherein the first conductive structure is electrically connected to the chip structure and comprises;

a first transition layer over the chip structure;

a first conductive layer on the first transition layer, wherein the first conductive layer is substantially made of twinned copper; and

a second conductive layer over the first conductive layer, wherein a first average roughness of a first top surface of the second conductive layer is less than a second average roughness of a second top surface of the first conductive layer.

2. The semiconductor package structure as claimed in claim 1, wherein the twinned copper in the first conductive layer comprises (111)-oriented twinned copper.

3. The semiconductor package structure as claimed in claim 1, further comprising:

a first dielectric layer over the chip structure, wherein the first conductive structure is over the first dielectric layer and extends through the first dielectric layer to be electrically connected to the chip structure, and the first dielectric layer is in direct contact with the chip structure and the first conductive structure.

4. The semiconductor package structure as claimed in claim 1, wherein the first conductive structure further comprises:

a seed layer between the chip structure and the first transition layer, wherein the seed layer is in direct contact with the chip structure and the first transition layer.

5. The semiconductor package structure as claimed in claim 1, further comprising:

a second conductive structure over and electrically connected to the first conductive structure, wherein the second conductive structure comprises;

a second transition layer over the first conductive structure, and

a third conductive layer on the second transition layer, the third conductive layer being substantially made of twinned copper.

6. The semiconductor package structure as claimed in claim 5, wherein:

the first and second conductive structures are configured as conductive lines; and

a first average line width of the first conductive structure is less than a second average line width of the second conductive structure, and the second conductive structure is in direct contact with the first conductive structure.

7. The semiconductor package structure as claimed in claim 1, wherein a thickness of the first conductive layer is greater than a thickness of the second conductive layer.

8. The semiconductor package structure as claimed in claim 7, wherein the first conductive layer is in direct contact with the second conductive layer and the first transition layer.

9. The semiconductor package structure as claimed in claim 1, wherein the first transition layer comprises twinned copper, and a twinned-copper volume percentage in the first transition layer increases toward the first conductive layer.

10. The semiconductor package structure as claimed in claim 1, wherein a thickness of the first conductive layer is greater than a thickness of the first transition layer.

11. A semiconductor package structure, comprising:

a chip structure;

a molding layer surrounding the chip structure;

a conductive via structure passing through the molding layer; and

a redistribution structure over the conductive via structure and the molding layer, wherein the redistribution structure is connected to the conductive via structure and comprises;

a first transition layer;

a first conductive layer over the first transition layer, wherein the first conductive layer is substantially made of twinned copper; and

a second conductive layer over the first conductive layer, wherein the second conductive layer is substantially made of twinned copper, and an average volume percentage of the twinned copper in the first conductive layer is greater than an average volume percentage of the twinned copper in the second conductive layer.

12. The semiconductor package structure as claimed in claim 11, wherein the conductive via structure comprises a second transition layer, and a third conductive layer over the second transition layer, the third conductive layer being substantially made of twinned copper.

13. The semiconductor package structure as claimed in claim 11, wherein the first conductive layer is in direct contact with the first transition layer.

14. The semiconductor package structure as claimed in claim 13, wherein the first conductive layer is in direct contact with the second conductive layer.

15. The semiconductor package structure as claimed in claim 11, further comprising:

a dielectric layer over and in direct contact with the chip structure and the molding layer, wherein the redistribution structure is over the dielectric layer and extends through the dielectric layer to be electrically connected to the conductive via structure.

16. The semiconductor package structure as claimed in claim 11, wherein the first conductive layer is thicker than the second conductive layer.

17. A semiconductor package structure, comprising:

a chip structure; and

a conductive structure over the chip structure, wherein the conductive structure is electrically connected to the chip structure and comprises;

a transition layer over the chip structure, wherein the transition layer comprises twinned copper; and

a first conductive layer on the transition layer, wherein the first conductive layer is substantially made of twinned copper, and an average volume percentage of the twinned copper in the first conductive layer is greater than an average volume percentage of the twinned copper in the transition layer.

18. The semiconductor package structure as claimed in claim 17, wherein the first conductive layer is thicker than the transition layer.

19. The semiconductor package structure as claimed in claim 17, wherein the conductive structure further comprises:

a seed layer between the chip structure and the transition layer, wherein the seed layer is in direct contact with the chip structure and the transition layer.

20. The semiconductor package structure as claimed in claim 17, wherein the conductive structure further comprises:

a second conductive layer over the first conductive layer, wherein the second conductive layer is substantially made of twinned copper, and the first conductive layer is thicker than the second conductive layer.