SEMICONDUCTOR PACKAGE

• US 20200135683A1
• Filed: 07/15/2019
• Published: 04/30/2020
• Est. Priority Date: 10/24/2018
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Sun Chul, Kim, Tae Hun, Hwang, Ji Hwan
• Granted Patent: US 10,971,470 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/02331 Multilayer structure
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/0346 Plating
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05616 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/05624 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05666 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05684 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05686 : with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/06181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/08 : of an individual bonding area
• CPC Class Codes: H01L 2224/08145 : the bodies being stacked
• CPC Class Codes: H01L 2224/08146 : the bonding area connecting to a via connection in the body
• CPC Class Codes: H01L 2224/08237 : the bonding area connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/085 : Material
• CPC Class Codes: H01L 2224/09181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13124 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16237 : the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/2919 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32 : of an individual layer connector
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 : the item being metallic
• CPC Class Codes: H01L 2224/45099 : Material
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73251 : on different surfaces
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/80001 : by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 2224/80006 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/80013 : Plasma cleaning
• CPC Class Codes: H01L 2224/80357 : being flush with the surface
• CPC Class Codes: H01L 2224/80895 : between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/80896 : between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/9202 : Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/107 : Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
• CPC Class Codes: H01L 23/36 : Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/09 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/0496 : 6th Group
• CPC Class Codes: H01L 2924/1816 : Exposing the passive side of the semiconductor or solid-state body

Abstract

A semiconductor package includes a first semiconductor chip including a body portion, a first bonding layer disposed on a first surface of the body portion, and through vias passing through at least a portion of the body portion; and a first redistribution portion disposed in the first semiconductor chip to be connected to the first semiconductor chip through the first bonding layer, the first redistribution portion including first redistribution layers electrically connected to the first semiconductor chip, a first wiring insulating layer disposed between the first redistribution layers, and a second bonding layer connected to the first bonding layer. The first bonding layer and the second bonding layer include first and metal pads disposed to correspond to each other and bonded to each other, respectively, and a first insulating layer and a second bonding insulating layer surrounding the first metal pads and the second metal pads, respectively.

Claims

1. A semiconductor package comprising:

a first semiconductor chip including a body portion, a first bonding layer disposed on a first surface of the body portion, and through vias passing through at least a portion of the body portion; and

a first redistribution portion disposed in a lower portion of the first semiconductor chip to be connected to the first semiconductor chip through the first bonding layer, the first redistribution portion including first redistribution layers electrically connected to the first semiconductor chip, at least one first wiring insulating layer disposed between the first redistribution layers, and a second bonding layer connected to the first bonding layer,

wherein the first bonding layer and the second bonding layer include first metal pads and second metal pads disposed to correspond to each other and bonded to each other, respectively, and a first insulating layer and a second bonding insulating layer surrounding the first metal pads and the second metal pads, respectively.

2. The semiconductor package of claim 1, wherein the first semiconductor chip has a first size substantially the same as a second size of the semiconductor package on a plane.

3. The semiconductor package of claim 1, wherein a side surface of the first semiconductor chip is exposed externally.

4. The semiconductor package of claim 1, wherein the through vias are electrically connected to the first metal pads through element layers of the first semiconductor chip.

5. The semiconductor package of claim 1, further comprising:

connection terminals disposed on a lower surface of the first redistribution portion, and electrically connected to the first redistribution layers.

6. The semiconductor package of claim 5, wherein the first redistribution portion further includes first vias that are vertically disposed and connect the first redistribution layers, and

an electrical signal from the first semiconductor chip is transmitted to the connection terminals through the first metal pads of the first bonding layer, the second metal pads of the second bonding layer, the first redistribution layers, and the first vias.

7. The semiconductor package of claim 1, further comprising:

a second redistribution portion disposed on a surface of the first semiconductor chip, opposing the first surface, the second redistribution portion including a second wiring insulating layer and at least one second redistribution layer connected to the through vias.

8. The semiconductor package of claim 7, further comprising:

at least one second semiconductor chip disposed on the second redistribution portion, and electrically connected to the first redistribution portion through the second redistribution portion.

9. The semiconductor package of claim 8, wherein the second redistribution portion further includes a third bonding layer disposed on a surface connected to the at least one second semiconductor chip,

the at least one second semiconductor chip further includes a fourth bonding layer disposed on a surface connected to the second redistribution portion, and

the third bonding layer and the fourth bonding layer include third metal pads and fourth metal pads, disposed to correspond to each other and bonded to each other, respectively, and a third bonding insulating layer and a fourth bonding insulating layer, surrounding the third metal pads and the fourth metal pads, respectively.

10. The semiconductor package of claim 8, wherein the at least one second semiconductor chip is provided as a plurality of second semiconductor chips disposed to be vertically stacked.

11. The semiconductor package of claim 10, wherein the plurality of second semiconductor chips include fifth bonding layers including fifth metal pads on surfaces, facing each other, respectively, and are bonded and connected to each other by the fifth bonding layers.

12. The semiconductor package of claim 8, wherein the first semiconductor chip is a logic semiconductor chip, and the at least one second semiconductor chip is a memory semiconductor chip.

13. The semiconductor package of claim 1, wherein the first surface of the first semiconductor chip is an active surface.

14. The semiconductor package of claim 1, wherein the first metal pads and the second metal pads include at least one among tungsten (W), aluminum (Al), copper (Cu), tungsten nitride (WN), tantalum nitride (TaN), and titanium nitride (TiN), and

the first insulating layer and second bonding insulating layer include at least one among SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

15. The semiconductor package of claim 1, further comprising:

a core layer disposed to surround at least a portion of the first semiconductor chip on the first redistribution portion.

16. A semiconductor package comprising:

a semiconductor chip including a first bonding layer disposed on a surface thereof; and

a redistribution portion disposed on the surface of the semiconductor chip and connected to the semiconductor chip through the first bonding layer, the redistribution portion including redistribution layers electrically connected to the semiconductor chip, at least one wiring insulating layer disposed between the redistribution layers, and a second bonding layer connected to the first bonding layer,

wherein the first bonding layer and the second bonding layer include first metal pads and second metal pads, disposed to correspond to each other and bonded to each other, respectively, and a first insulating layer and a second bonding insulating layer, surrounding the first metal pads and the second metal pads, respectively, and

the entirety of the redistribution layers are disposed to overlap the semiconductor chip on a plane.

17. The semiconductor package of claim 16, wherein a side surface of the semiconductor chip is exposed externally.

18. The semiconductor package of claim 16, wherein the semiconductor chip further includes through vias passing through an upper surface and a lower surface of the semiconductor chip, and

the through vias are electrically connected to the first bonding layer at one end of the through vias.

19. The semiconductor package of claim 16, further comprising:

a heat dissipation layer disposed on the semiconductor chip.

20. A semiconductor package comprising:

a first semiconductor chip including first metal pads disposed on a surface and through vias passing through at least a portion of the first semiconductor chip;

a first redistribution portion disposed in a lower portion of the first semiconductor chip, and including second metal pads bonded to the first metal pads and a first redistribution layer electrically connected to the first semiconductor chip;

a second redistribution portion disposed in an upper portion of the first semiconductor chip, and including a second redistribution layer electrically connected to the first semiconductor chip and third metal pads disposed on an upper surface of the second redistribution portion; and

at least one second semiconductor chip disposed on the second redistribution portion, and in which fourth metal pads are disposed of a surface thereof, the fourth metal pads being bonded to the third metal pads.

21-24. -24. (canceled)