SEMICONDUCTOR PACKAGE

• US 20200135684A1
• Filed: 07/19/2019
• Published: 04/30/2020
• Est. Priority Date: 10/24/2018
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KIM, Sun Chul, KIM, Tae Hun, HWANG, Ji Hwan
• Application Number:
  US16/517,007
• Publication Number:
  US 20200135684A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/06131 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/06135 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/08 of an individual bonding area
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/08146 the bonding area connecting to a via connection in the body
• CPC Class Codes: H01L 2224/08225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/0823 the bonding area connecting to a pin of the item
• CPC Class Codes: H01L 2224/09181 On opposite sides of the body
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/14131 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/14135 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16238 : the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/32 : of an individual layer connector
• CPC Class Codes: H01L 2224/32245 : the item being metallic
• CPC Class Codes: H01L 2224/73251 : on different surfaces
• CPC Class Codes: H01L 2224/80001 : by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 2224/80013 : Plasma cleaning
• CPC Class Codes: H01L 2224/80357 : being flush with the surface
• CPC Class Codes: H01L 2224/80895 : between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/80896 : between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/9202 : Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/9222 : Sequential connecting processes
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/09 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/33 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/18161 : of a flip chip

Abstract

A semiconductor package includes a first semiconductor chip including a first bonding layer, on one surface, and a chip structure stacked on the first semiconductor chip and including a second bonding layer on a surface facing the first semiconductor chip and a plurality of second semiconductor chips. The plurality of second semiconductor chips includes a chip area and a scribe area outside of the chip area, respectively, the plurality of second semiconductor chips being connected to each other by the scribe area in the chip structure. The first and second bonding layers include first and second metal pads disposed to correspond to each other and bonded to each other, respectively and first and second bonding insulating layers surrounding the first and second metal pads, respectively.

Claims

1. A semiconductor package, comprising:

a first semiconductor chip including a first bonding layer on a surface; and

a chip structure stacked on the first semiconductor chip and including a second bonding layer on a surface facing the first semiconductor chip and a plurality of second semiconductor chips, wherein;

the plurality of second semiconductor chips include a chip area and a scribe area outside of the chip area, respectively, the plurality of second semiconductor chips being connected to each other by the scribe area in the chip structure, and

the first and second bonding layers include first and second metal pads disposed to correspond to each other and bonded to each other, respectively, and first and second bonding insulating layers surrounding the first and second metal pads, respectively.

2. The semiconductor package as claimed in claim 1, wherein the plurality of second semiconductor chips form the chip structure without being sawed from each other.

3. The semiconductor package as claimed in claim 1, wherein the chip structure has substantially the same size as the first semiconductor chip on a plane.

4. The semiconductor package as claimed in claim 1, wherein side surfaces of the chip structure are exposed externally.

5. The semiconductor package as claimed in claim 1, wherein the first semiconductor chip includes a device area in which semiconductor devices are disposed and a via area on at least one side of the device area, the via area being provided with first through vias disposed therein electrically connecting the chip structure and the first semiconductor chip.

6. The semiconductor package as claimed in claim 5, wherein the first semiconductor chip further includes a substrate on an entirety of the device area and the via area.

7. The semiconductor package as claimed in claim 5, wherein the via area is disposed to surround the device area on a plane.

8. The semiconductor package as claimed in claim 5, wherein the via area includes a plurality of areas disposed to be spaced apart from each other along a perimeter of the device area on a plane.

9. The semiconductor package as claimed in claim 5, wherein the chip structure further includes second through vias disposed in an area overlapping the via area.

10. The semiconductor package as claimed in claim 1, wherein:

the chip structure includes first and second chip structures stacked vertically,

the first chip structure is disposed in a lower portion and includes the second bonding layer and a third bonding layer, and the second chip structure is disposed in an upper portion and includes a fourth bonding layer connected to the third bonding layer, and

the third and fourth bonding layers includes third and fourth metal pads disposed to correspond to each other and bonded to each other, respectively, and third and fourth bonding insulating layers surrounding the third and fourth metal pads, respectively.

11. The semiconductor package as claimed in claim 10, wherein the third and fourth bonding layers are on active surfaces of the second semiconductor chips in the first and second chip structures, respectively.

12. The semiconductor package as claimed in claim 10, wherein the third bonding layer is on inactive surfaces of the second semiconductor chips in the first chip structure, and the fourth bonding layer is on active surfaces of the second semiconductor chips in the second chip structure.

13. The semiconductor package as claimed in claim 1, wherein the first and second bonding layers are directly bonded and are in contact with each other.

14. The semiconductor package as claimed in claim 1, wherein:

the first and second metal pads include at least one of tungsten, aluminum, copper, tungsten nitride, tantalum nitride, and titanium nitride, and

the first and second bonding insulating layers include at least one of SiO, SiN, SiCN, SiOC, SiON and SiOCN.

15. A semiconductor package, comprising:

a first semiconductor chip including a first bonding layer on a surface, and having a device area in which semiconductor devices are disposed and a via area on at least one side of the device area, the via area being provided with through vias disposed therein; and

a chip structure stacked on the first semiconductor chip and bonded to the first semiconductor chip through the first bonding layer, and including a second bonding layer connected to the first bonding layer and a plurality of second semiconductor chips,

wherein the plurality of second semiconductor chips include a chip area and a scribe area outside of the chip area, respectively, the plurality of second semiconductor chips being connected to each other by the scribe area in the chip structure.

16. The semiconductor package as claimed in claim 15, wherein the through vias penetrate the first semiconductor chip and are electrically connected to the chip structure.

17. The semiconductor package as claimed in claim 15, wherein the device area and the via area have an upper surface and a lower surface that are coplanar in the first semiconductor chip.

18. A semiconductor package, comprising:

a first semiconductor chip including first metal pads on a surface;

a first redistribution portion on the first semiconductor chip and including a first redistribution layer electrically connected to the first semiconductor chip and second metal pads on a lower surface thereof and bonded to the first metal pads; and

a chip structure on the first redistribution portion and including a plurality of second semiconductor chips,

wherein the first semiconductor chip has a size that is substantially the same as a size of the chip structure on a plane.

19. The semiconductor package as claimed in claim 18, wherein:

the plurality of second semiconductor chips include a chip area and a scribe area outside of the chip area, respectively, the plurality of second semiconductor chips being connected to each other by the scribe area in the chip structure, and

the chip area and scribe area are on one substrate.

20. The semiconductor package as claimed in claim 18, further comprising a second redistribution portion disposed in a lower portion of the first semiconductor chip and including a second redistribution layer electrically connected to the first semiconductor chip.