SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20200135687A1
• Filed: 09/19/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: IKURA, Kenji, ISHII, Hideki, MAEDA, Takehiko, KATO, Takeumi
• Granted Patent: US 11,270,971 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05073 Single internal layer
• CPC Class Codes: H01L 2224/05083 Three-layer arrangements
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/08503 comprising an intermetallic compound
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48453 of the interface with the bonding area
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/48507 comprising an intermetallic compound
• CPC Class Codes: H01L 2224/4852 Bonding interface between the connecting portion and the bonding area
• CPC Class Codes: H01L 2224/48824 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/78303 of the pressing surface, e.g. tip or head
• CPC Class Codes: H01L 2224/85181 : connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
• CPC Class Codes: H01L 2224/85205 : Ultrasonic bonding
• CPC Class Codes: H01L 2224/85207 : Thermosonic bonding
• CPC Class Codes: H01L 2224/85395 : having an external coating, e.g. protective bond-through coating
• CPC Class Codes: H01L 2224/8581 : involving forming an intermetallic compound at the bonding interface
• CPC Class Codes: H01L 2224/85948 : Thermal treatments, e.g. annealing, controlled cooling
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

A semiconductor device capable of suppressing propagation of a crack caused by a temperature cycle at a bonding part between a bonding pad and a bonding wire is provided. A semiconductor device according to an embodiment includes a semiconductor chip having bonding pads and bonding wires. The bonding pad includes a barrier layer and a bonding layer formed on the barrier layer and formed of a material containing aluminum. The bonding wire is bonded to the bonding pad and formed of a material containing copper. An intermetallic compound layer formed of an intermetallic compound containing copper and aluminum is formed so as to reach the barrier layer from the bonding wire in at least a part of the bonding part between the bonding pad and the bonding wire.

Claims

1. A semiconductor device, comprising:

a semiconductor chip having a bonding pad which includes a barrier layer and a bonding layer formed on the barrier layer, and the bonding pad formed of a material containing aluminum; and

a bonding wire bonded to the bonding pad and formed of a material containing copper,

wherein an intermetallic compound layer formed of an intermetallic compound containing copper from the bonding wire and aluminum from the bonding pad is formed such that at least a portion of the intermetallic compound layer reaches the barrier layer.

2. The semiconductor device according to claim 1,

wherein the portion of the intermetallic compound layer reaching from the bonding wire to the barrier layer is disposed along an outer periphery of the copper wire.

3. The semiconductor device according to claim 1,

wherein the barrier layer is formed of a material containing titanium or tantalum.

4. The semiconductor device according to claim 1,

wherein the thickness of the barrier layer is greater than or equal to 0.03 μ

m and less than 0.2 μ

m.

5. The semiconductor device according to claim 1,

wherein the semiconductor chip further includes a first interlayer insulating film and a first wiring formed in the first interlayer insulating film,

wherein the bonding pad is formed on the first interlayer insulating film, and

wherein the first wiring is formed at a position not overlapping with the bonding pad in plan view.

6. The semiconductor device according to claim 5,

wherein the semiconductor chip further includes a second interlayer insulating film and a second wiring formed in the second interlayer insulating film,

wherein the first interlayer insulating film is formed on the second interlayer insulating film, and the second wiring is formed at a position not overlapping the bonding pad in plan view.

7. The semiconductor device according to claim 1,

wherein the bonding pad further comprises a base layer, and the barrier layer is formed on the base layer.

8. The semiconductor device according to claim 7,

wherein the base layer is formed of a material containing aluminum.

9. A method of manufacturing a semiconductor device, comprising the steps of:

(a) providing a semiconductor chip having a bonding pad formed on a barrier layer and including a bonding layer formed of a material containing aluminum; and

(b) bonding a bonding wire formed of a material containing copper to the bonding pad,

wherein an intermetallic compound layer formed of an intermetallic compound containing copper from the bonding wire and aluminum from bonding pad is formed such that at least a portion of the intermetallic compound layer reaches the barrier layer.

10. The method of manufacturing a semiconductor device according to claim 9, further comprising the steps of:

(c) after the step (b), sealing with resin the semiconductor chip and the bonding wire; and

(d) after the step (c), performing a burn-in test on the semiconductor chip,

wherein in the step (b), the bonding wire is bonded to the bonding pad, and

wherein, in the step (b), the bonding layer remains between the bonding wire and the barrier layer.

11. The method of manufacturing a semiconductor device according to claim 10,

wherein the step (b) further comprises a heating step of heating the semiconductor chip on which the wire bonding has been performed.

12. The method of manufacturing a semiconductor device according to claim 11,

wherein the heating is performed before the step (c).

13. The method for manufacturing a semiconductor device according to claim 9,

wherein the thickness of the bonding layer is 0.01 μ

m or more and 2 μ

m or less.