WAFER-LEVEL PACKAGING METHODS USING A PHOTOLITHOGRAPHIC BONDING MATERIAL

• US 20200135689A1
• Filed: 12/30/2018
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Ningbo Semiconductor International Corporation (Semiconductor Manufacturing International Corporation)
• Original Assignee: Ningbo Semiconductor International Corporation (Semiconductor Manufacturing International Corporation)
• Inventors: SHI, Hu, LIU, Mengbin
• Granted Patent: US 10,755,979 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/27 Manufacturing methods
• CPC Class Codes: H01L 2224/271 Manufacture and pre-treatment of the layer connector preform
• CPC Class Codes: H01L 2224/27436 Lamination of a preform, e.g. foil, sheet or layer
• CPC Class Codes: H01L 2224/27515 Curing and solidification, e.g. of a photosensitive layer material
• CPC Class Codes: H01L 2224/27618 with selective exposure, development and removal of a photosensitive layer material, e.g. of a photosensitive conductive resin
• CPC Class Codes: H01L 2224/29034 the layer connector covering only portions of the surface to be connected
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32105 the layer connector connecting bonding areas being not aligned with respect to each other
• CPC Class Codes: H01L 2224/32106 the layer connector connecting one bonding area to at least two respective bonding areas
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/75101 Chamber
• CPC Class Codes: H01L 2224/75251 in the lower part of the bonding apparatus, e.g. in the apparatus chuck
• CPC Class Codes: H01L 2224/75252 in the upper part of the bonding apparatus, e.g. in the bonding head
• CPC Class Codes: H01L 2224/753 by means of pressure
• CPC Class Codes: H01L 2224/75745 in the upper part of the bonding apparatus, e.g. in the bonding head
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/83048 Thermal treatments, e.g. annealing, controlled pre-heating or pre-cooling
• CPC Class Codes: H01L 2224/83203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/83204 : with a graded temperature profile
• CPC Class Codes: H01L 2224/83862 : Heat curing
• CPC Class Codes: H01L 2224/83907 : Intermediate bonding, i.e. intermediate bonding step for temporarily bonding the semiconductor or solid-state body, followed by at least a further bonding step
• CPC Class Codes: H01L 2224/83951 : Forming additional members, e.g. for reinforcing, fillet sealant
• CPC Class Codes: H01L 2224/83986 : Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
• CPC Class Codes: H01L 2224/92 : Specific sequence of method steps
• CPC Class Codes: H01L 2224/9202 : Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/9211 : Parallel connecting processes
• CPC Class Codes: H01L 2224/92144 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/92242 : the first connecting process involving a layer connector
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/75 : Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/07025 : Polyimide
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A wafer-level packaging method using a photolithographic bonding material includes providing a base substrate; providing a plurality of first chips; forming a photolithographic bonding layer on the base substrate or on the first chips; forming a plurality of first vias in the photolithographic bonding layer; pre-bonding the first chips to the base substrate through the photolithographic bonding layer with each first chip corresponding to a first via; using a thermal compression bonding process to bond the first chips to the base substrate such that an encapsulation material fills between adjacent first chips and covers the first chips and the base substrate; etching the base substrate to form a plurality of second vias through the base substrate with each second via connected to a first via to form a first conductive via; and forming a first conductive plug in the first conductive via to electrically connect to a corresponding first chip.

Claims

1. A wafer-level packaging method using a photolithographic bonding material, comprising:

providing a base substrate;

providing a plurality of first chips;

forming a photolithographic bonding layer on the base substrate or on the plurality of first chips;

forming a plurality of first vias in the photolithographic bonding layer by patterning the photolithographic bonding layer;

pre-bonding the plurality of first chips to the base substrate through the photolithographic bonding layer, wherein each first chip of the plurality of first chips corresponds to a first via of the plurality of first vias;

providing an encapsulation material, and using a thermal compression bonding process to bond the plurality of first chips to the base substrate such that the encapsulation material fills up space between adjacent first chips and covers the plurality of first chips and the base substrate;

after bonding the plurality of first chips to the base substrate, etching the base substrate from a surface that faces away from the plurality of first chips to form a plurality of second vias passing through the base substrate, wherein, each second via of the plurality of second vias is connected to a first via of the plurality of first vias to form a first conductive via; and

forming a first conductive plug in the first conductive via to electrically connect to a corresponding first chip.

2. The packaging method according to claim 1, wherein:

the plurality of first chips is integrated in a first device wafer;

the photolithographic bonding layer is formed on the first device wafer; and

after forming the plurality of first vias and prior to pre-bonding the plurality of first chips to the base substrate, the method further includes;

dicing the first device wafer to obtain a plurality of discrete first chips.

3. The packaging method according to claim 2, wherein:

the first device wafer includes a plurality of device regions and a scribe line region surrounding the plurality of device regions;

forming the plurality of first vias by patterning the photolithographic bonding layer includes forming an opening in the photolithographic bonding layer to expose a portion of the first device wafer in the scribe line region.

4. The packaging method according to claim 1, wherein:

the plurality of first chips is unintegrated and is separated from each other.

5. The packaging method according to claim 1, wherein pre-bonding the plurality of first chips to the base substrate through the photolithographic bonding layer includes:

performing a pre-heating process on the plurality of first chips and the base substrate; and

after performing the pre-heating process, performing a first pressing process through one or both of the plurality of first chips and the base substrate; and

when performing the first pressing process, simultaneously performing a first heating process on the plurality of first chips and the base substrate.

6. The packaging method according to claim 5, wherein:

during the first pressing process, the plurality of first chips is pressed from a surface that faces away from the base substrate;

or

during the first heating process, the plurality of first chips is heated from the surface that faces away from the base substrate, and the base substrate is heated from a surface that faces away from the plurality of first chips.

7. The packaging method according to claim 1, wherein using the thermal compression bonding process to bond the plurality of first chips to the base substrate includes:

performing a vacuum process and a second heating process to bring a process pressure of the thermal compression bonding process to a preset pressure and a process temperature of the thermal compression bonding process to a preset temperature;

bringing the plurality of first chips to be in contact with the encapsulation material;

under the preset pressure and the process temperature, performing a second pressing process on the base substrate and the encapsulation material for a preset time, wherein;

after the second pressing process, the encapsulation material fills up the space between adjacent first chips and covers the plurality of first chips and the base substrate, and the plurality of first chips is bonded to the base substrate, and

after the second pressing process, performing a thermal solidification process on the encapsulation material at the preset temperature.

8. The packaging method according to claim 7, wherein:

the base substrate is a second device wafer, wherein a plurality of second chips is integrated in the second device wafer, a plurality of first soldering pads is formed in the plurality of second chips, a surface of the second device wafer exposing the plurality of first soldering pads is a wafer front side, and a surface of the second device wafer in opposite to the wafer front side is a wafer back side; and

after performing the thermal compression bonding process, and prior to etching the base substrate from the surface that faces away from the first chip, the packaging method further includes performing a thinning-down process on the wafer back side.

9. The packaging method according to claim 1, wherein:

the photolithographic bonding layer is formed through a lamination process.

10. The packaging method according to claim 1, wherein:

the photolithographic bonding layer is made of a photolithographic dry film, or a material including photolithographic polyimide, photolithographic polybenzoxazole (PBO), or photolithographic benzocyclobutene (BCB).

11. The packaging method according to claim 1, wherein:

the encapsulation material is a film type encapsulation material, a liquid encapsulation material, or a powdered encapsulation material.

12. The packaging method according to claim 1, wherein:

etching the base substrate from the surface that faces away from the plurality of first chips includes performing a dry etching process, a wet etching process, or a processing combining both dry etching and wet etching.

13. The packaging method according to claim 1, wherein:

the thermal compression bonding process is a thermal compression molding process or a thermal lamination process.

14. The packaging method according to claim 5, wherein when pre-bonding the plurality of first chips to the base substrate through the photolithographic bonding layer, process parameters adopted include:

a process temperature of the pre-heating process in a range of approximately 150°

C. to 250°

C.;

a process time of the pre-heating process in a range of approximately 1 minute to 5 minutes;

a pressure applied in the first pressing process in a range of approximately 100 N to 800 N;

a process temperature of the first heating process in a range of approximately 150°

C. to 250°

C.; and

a process time of the first heating process in a range of approximately 1 second to 60 seconds.

15. The packaging method according to claim 7, wherein when performing the thermal compression bonding process, process parameters adopted include:

the preset pressure in a range of approximately 5 kPa to 15 kPa;

the preset temperature in a range of approximately 120°

C. to 180°

C.;

the pressure applied in the second pressing process in a range of approximately 0.1 MPa to 10 MPa;

the preset time in a range of approximately 30 seconds to 60 seconds; and

a process time of the thermal solidification in a range of approximately 300 seconds to 600 seconds.

16. The packaging method according to claim 1, wherein the plurality of first vias is formed in the photolithographic bonding layer through a photolithography process, and process parameters adopted in the photolithography process include:

an exposure energy in a range of approximately 80 mJ/cm² to 150 mJ/cm²;

a process temperature of a post-exposure baking (PEB) process in a range of approximately 40°

C. to 100°

C.;

a process time of the PEB process in a range of approximately 3 minutes to 10 minutes; and

a development time in a range of approximately 4 minutes to 7 minutes.

17. The packaging method according to claim 1, wherein:

a second soldering pad is formed in each first chip of the plurality of first chips; and

the second soldering pad is exposed by a first via of the plurality of first vias that corresponds to the first chip of the plurality of first chips.

18. The packaging method according to claim 8, wherein:

after performing the thermal compression bonding process, the method further includes etching the base substrate from the surface that faces away from the plurality of first chips to form a plurality of second conductive vias in the base substrate; and

when forming the first conductive plug in each first conductive via of the plurality of first vias, the method also includes forming a second conductive plug in each second conductive via of the plurality of second conductive vias to electrically connect to the second chip.

19. The packaging method according to claim 1, wherein:

the base substrate is a second device wafer, a carrier wafer, or a panel.

20. The packaging method according to claim 1, wherein:

the base substrate is a second device wafer, wherein a plurality of second chips is integrated in the second device wafer, a plurality of first soldering pads is formed in the plurality of second chips, a surface of the second device wafer exposing the plurality of first soldering pads is a wafer front side, and a surface of the second device wafer in opposite to the wafer front side is a wafer back side; and

the plurality of first chips is pre-bonded to the wafer front side or the wafer back side of the base substrate.