SEMICONDCUTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

• US 20200135692A1
• Filed: 12/13/2019
• Published: 04/30/2020
• Est. Priority Date: 10/28/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Shih-Wei, Chen, Chih-Hua, Pan, Hsin-Yu, Tsai, Hao-Yi, Chuang, Lipu Kris, Kuo, Tin-Hao
• Granted Patent: US 10,811,384 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68318 Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/1624 the bump connector connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/21 of an individual HDI interconnect
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/2929 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/29393 with a principal constituent of the material being a solid not provided for in groups H01L2224/293 - H01L2224/29391, e.g. allotropes of carbon, fullerene, graphite, carbon-nanotubes, diamond
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32245 : the item being metallic
• CPC Class Codes: H01L 2224/73203 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73217 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/814 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/83424 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/83447 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/83486 : with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06562 : at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06586 : Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/295 : containing a filler H01L23/296 takes precedence
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/367 : Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/3675 : characterised by the shape of the housing
• CPC Class Codes: H01L 23/3731 : Ceramic materials or glass H01L23/3732, H01L23/3733, H01L23/3735, H01L23/3737, H01L23/3738 take precedence
• CPC Class Codes: H01L 23/3736 : Metallic materials H01L23/3732, H01L23/3733, H01L23/3735, H01L23/3737, H01L23/3738 take precedence
• CPC Class Codes: H01L 23/3738 : Semiconductor materials
• CPC Class Codes: H01L 23/4334 : Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/5383 : Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/05432 : Al2O3
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16251 : Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A semiconductor package includes a redistribution structure, at least one semiconductor device, a heat dissipation component, and an encapsulating material. The at least one semiconductor device is disposed on and electrically connected to the redistribution structure. The heat dissipation component is disposed on the redistribution structure and includes a concave portion for receiving the at least one semiconductor device and an extending portion connected to the concave portion and contacting the redistribution structure, wherein the concave portion contacts the at least one semiconductor device. The encapsulating material is disposed over the redistribution structure, wherein the encapsulating material fills the concave portion and encapsulates the at least one semiconductor device.

Claims

1. A semiconductor package, comprising:

a heat dissipation component comprising a concave portion;

at least one semiconductor device disposed in the concave portion of the heat dissipation component;

an encapsulating material filling the concave portion and encapsulating the at least one semiconductor device; and

a redistribution structure disposed on the heat dissipation component, the at least one semiconductor device, and the encapsulating material, wherein the redistribution structure is electrically connected to the semiconductor device.

2. The semiconductor package as claimed in claim 1, wherein the heat dissipation component further comprising an extending portion connected to the concave portion, wherein the extending portion of the heat dissipation component is thermally coupled to the redistribution structure.

3. The semiconductor package as claimed in claim 1, wherein the extending portion of the heat dissipation component is in contact with the redistribution structure.

4. The semiconductor package as claimed in claim 3, wherein the extending portion of the heat dissipation component comprises a surface in contact with the redistribution structure, and the surface of the extending portion is substantially level with a surface of the encapsulating material.

5. The semiconductor package as claimed in claim 3, wherein the extending portion of the heat dissipation component is in directly contact with an upmost redistribution circuit layer of the redistribution structure.

6. The semiconductor package as claimed in claim 1, wherein the extending portion of the heat dissipation component is thermally coupled to the redistribution structure through an interface material encapsulated by the encapsulating material.

7. The semiconductor package as claimed in claim 6, wherein the interface material comprises a surface in contact with the redistribution structure, and the surface of the interface material is substantially level with a surface of the encapsulating material.

8. The semiconductor package as claimed in claim 1, wherein the concave portion of the heat dissipation component is thermally coupled to the at least one semiconductor device through an interface material.

9. The semiconductor package as claimed in claim 1, wherein the heat dissipation component comprises cutouts penetrating the heat dissipation component.

10. The semiconductor package as claimed in claim 1 further comprising electrical connectors, wherein the electrical connectors are electrically connected to the at least one semiconductor device through the redistribution structure.

11. A method, comprising:

disposing at least one semiconductor device in a concave portion of a heat dissipation component;

encapsulating the at least one semiconductor device and filling the concave portion of the heat dissipation component with an encapsulating material; and

forming a redistribution structure over the encapsulating material and the heat dissipation component, wherein the redistribution structure is thermally coupled to the heat dissipation component and is electrically connected to the at least one semiconductor device.

12. The method as claimed in claim 11, wherein the at least one semiconductor device is disposed in the concave portion of the heat dissipation component through an interface material between the concave portion and a back surface of the at least one semiconductor device.

13. The method as claimed in claim 11, wherein the at least one semiconductor device comprises a first semiconductor device and at least one second semiconductor device, and disposing the at least one semiconductor device in the concave portion of the heat dissipation component comprises:

disposing the at least one second semiconductor device in the concave portion, wherein the at least one second semiconductor device comprises an active surface and conductive pillars disposed on the active surface; and

stacking the first semiconductor device on the active surface of the at least one second semiconductor device.

14. The method as claimed in claim 13, wherein the at least one second semiconductor device comprises second semiconductor devices arranged in a side-by-side manner, and the first semiconductor device is stacked on the second semiconductor devices.

15. The method as claimed in claim 13, wherein the first semiconductor device is stacked on the at least one second semiconductor device through an interface material between the at least one second semiconductor device and a back surface of the first semiconductor device.

16. A method, comprising:

disposing at least one semiconductor device on a redistribution structure;

covering the at least one semiconductor device and the redistribution structure with a heat dissipation component, the heat dissipation component comprising a concave portion for receiving the at least one semiconductor device; and

encapsulating the at least one semiconductor device and filling concave portion with an encapsulating material.

17. The method as claimed in claim 16, wherein the heat dissipation component further comprises an extending portion connected to the concave portion, the extending portion of the heat dissipation component is thermally coupled to the redistribution structure through a first interface material, and the concave portion of the heat dissipation component is thermally coupled to a back surface of the at least one semiconductor device through a second interface material.

18. The method as claimed in claim 16, wherein the at least one semiconductor device comprises a first semiconductor device and at least one second semiconductor device, and disposing the at least one semiconductor device on the redistribution structure comprises:

mounting the first semiconductor device on the redistribution structure through conductive bumps; and

stacking the at least one second semiconductor device on the first semiconductor device, wherein the at least one second semiconductor device comprises an active surface facing the redistribution structure and conductive pillars disposed on the active surface, and the conductive pillars are configured to be disposed on the redistribution structure.

19. The method as claimed in claim 18, wherein the at least one second semiconductor device comprises second semiconductor devices arranged in a side-by-side manner.

20. The method as claimed in claim 16, wherein the encapsulating material is formed by a molding process followed by a polishing process.