SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF MAKING THE SAME

• US 20200135693A1
• Filed: 10/22/2019
• Published: 04/30/2020
• Est. Priority Date: 10/26/2018
• Status: Abandoned Application

• Current Assignee: Phoenix Pioneer Technology Co., Ltd.
• Original Assignee: Phoenix Pioneer Technology Co., Ltd.
• Inventors: Hu, Chu-Chin, Hsu, Shih-Ping, Hsu, Che-Wei
• Application Number:
  US16/659,716
• Publication Number:
  US 20200135693A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15172 : Fan-out arrangement of the internal vias
• CPC Class Codes: H01L 2924/18161 : of a flip chip

Abstract

A semiconductor package structure includes a circuit build-up substrate, a chip, a plurality of conductive pillar, a molding layer and at least a memory module. The circuit build-up substrate has a first surface. A plurality of flip-chip bonding pads and a plurality of first bonding pads are exposed from the first surface. The chip is electrically connected to the flip-chip bonding pads. The conductive pillars are disposed on the first surface of the circuit build-up substrate and electrically connected to the first bonding pads. The molding layer is disposed on the first surface of the circuit build-up substrate to cover the chip and the conductive pillars. A second side of the chip and a first end of each conductive pillar are exposed from the molding layer. The memory module is disposed on the molding layer and electrically connected to the first end of the conductive pillar.

Claims

1. A semiconductor package structure, comprising:

a circuit build-up substrate, which has opposite a first surface and a second surface, with the first surface exposing a plurality of flip-chip bonding pads and a plurality of first bonding pads, and the second surface exposing a plurality of second bonding pads;

a chip, which has opposite a first surface and a second surface, with the former facing the first surface of the circuit build-up substrate and electrically connected to such flip-chip bonding pads;

a plurality of conductive pillars, which has opposite a first end and a second end, with the second end arranged on the first surface of the circuit build-up substrate and electrically connected to the corresponding first bonding pads;

a molding layer, which is arranged on the first surface of the circuit build-up substrate to cover the chip and the conductive pillars, with the second surface of the chip and the first end of the conductive pillars exposed from the molding layer; and

at least a memory module, which is disposed on the molding layer and electrically connected to the first end of the conductive pillars,

wherein the chip and the memory module do not overlap in an orthographic projection direction.

2. The semiconductor package structure of claim 1, further comprising:

a conductive adhesive layer, which is arranged between the conductive pillars and the first bonding pads.

3. The semiconductor package structure of claim 1, further comprising:

a heat dissipation component, which is disposed on the memory module and/or on the second surface of the chip.

4. The semiconductor package structure of claim 1, wherein the circuit build-up substrate has at least one circuit build-up structure that has a conductor layer, a conductive pillars layer and a dielectric layer, with the conductor layer and the conductive pillars layer overlapping each other and embedded in the dielectric layer.

5. The semiconductor package structure of claim 1, wherein the first bonding pads of the circuit build-up substrate are located around the flip-chip bonding pads.

6. A manufacturing method for a semiconductor package structure, comprising:

providing a circuit build-up substrate, which has a first surface that exposes a plurality of flip-chip bonding pads and a plurality of first bonding pads located around the flip-chip bonding pads;

forming a conductive substrate embedded with a chip and a plurality of conductive pillars on the first surface of the circuit build-up substrate, in which the first surface the chip is disposed corresponding to the flip-chip bonding pads and the second end of the conductive pillars is disposed corresponding to the first bonding pads, wherein a second surface of the chip and a first end of each conductive pillars are exposed from an upper surface of the conductive substrates; and

arranging at least one memory module on the conductive substrate, corresponding to the first end of the conductive pillars, wherein the memory module and the chip do not overlap in an orthographic projection direction.

7. The manufacturing method of claim 6, wherein the step of forming the conductive substrate embedded with a chip and the conductive pillars, comprising:

arranging the conductive pillars on the first surface of the circuit build-up substrate with its second end corresponding to the first bonding pads;

disposing the chip on the first surface of the circuit build-up substrate with its first surface corresponding to such flip-chip bonding pads; and

forming a molding layer on the first surface of the circuit build-up substrate to cover the conductive pillars and chips and expose the first end of each conductive pillars and the second surface of the chip.

8. The manufacturing method of claim 7, wherein each conductive pillar is electrically connected to the corresponding first bonding pads by a conductive adhesive layer at the second end.

9. The manufacturing method of claim 7, wherein the step of arranging the conductive pillars, further comprising:

forming a patterned photoresistive layer on the first surface of the circuit build-up substrate and a plurality of blind holes to expose the first bonding pads;

forming a metal layer on the blind holes and exposing from the first bonding pads; and

removing the patterned photoresistive layer to form the conductive pillars and expose the flip-chip bonding pads.

10. The manufacturing method of claim 6, wherein the step of forming the conductive substrate embedded with the chip and the conductive pillars, comprising:

disposing the chip on the first surface of the circuit build-up substrate with its first surface corresponding to the flip-chip bonding pads;

forming a molding layer on the first surface of the circuit build-up substrate to cover the chip;

forming a plurality of openings on the molding layer which are corresponding to the first bonding pads;

forming a plurality of conductive pillars in the openings that are electrically connected to the corresponding first bonding pads; and

exposing the first end of each conductive pillar and the second surface of the chip from the molding layer.

11. The manufacturing method of claim 6, further comprising:

disposing a heat dissipation component on the second surface of the chip and/or on the memory module.