CHIP ON FILM PACKAGE

• US 20200135695A1
• Filed: 10/29/2018
• Published: 04/30/2020
• Est. Priority Date: 10/29/2018
• Status: Active Grant

• Current Assignee: Novatek Microelectronics Corporation (Novatek Microelectronics Corp Limited)
• Original Assignee: Novatek Microelectronics Corporation (Novatek Microelectronics Corp Limited)
• Inventors: Liao, Chun-Yu, Yu, Teng-Jui
• Granted Patent: US 11,189,597 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 23/4985 Flexible insulating substrates H01L23/49572 and H01L23/49855 take precedence
• CPC Class Codes: H01L 23/49894 Materials of the insulating layers or coatings
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5387 Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15313 being a land array, e.g. LGA
• CPC Class Codes: H01L 2924/15333 being a land array, e.g. LGA

Abstract

A chip on film package including a flexible film, a first patterned circuit layer, one or more first chips, a second patterned circuit layer, and one or more second chips. The flexible film includes a first surface and a second surface opposite to the first surface. The first patterned circuit layer is disposed on the first surface. The one or more first chips are mounted on the first surface and electrically connected to the first patterned circuit layer. The second patterned circuit layer is disposed on the second surface. The one or more second chips are mounted on the second surface and electrically connected to the second patterned circuit layer.

Claims

1. A chip on film package, comprising:

a flexible film comprising a first surface and a second surface opposite to the first surface;

a first patterned circuit layer disposed on the first surface;

one or more first chips mounted on the first surface and electrically connected to the first patterned circuit layer;

a second patterned circuit layer disposed on the second surface; and

one or more second chips mounted on the second surface and electrically connected to the second patterned circuit layer.

2. The chip on film package as claimed in claim 1, wherein the one or more first chips are mounted on a first mounting region of the first surface, the one or more second chips are mounted on a second mounting region of the second surface, and the first mounting region is overlapped with the second mounting region from a top view.

3. The chip on film package as claimed in claim 1, wherein at least one of the one or more second chips are located right under at least one of the one or more first chips.

4. The chip on film package as claimed in claim 1, wherein the one or more first chips are mounted on a first mounting region of the first surface, the one or more second chips are mounted on a second mounting region of the second surface, and the first mounting region is not overlapped with the second mounting region from a top view.

5. The chip on film package as claimed in claim 1, wherein the flexible film further comprises one or more vias electrically connecting the first patterned circuit layer and the second patterned circuit layer.

6. The chip on film package as claimed in claim 1, further comprising a first solder resist layer disposed on the first patterned circuit layer and exposing a part of the first patterned circuit layer where the one or more first chips are mounted.

7. The chip on film package as claimed in claim 1, further comprising a second solder resist layer disposed on the second patterned circuit layer and exposing a part of the second patterned circuit layer where the one or more second chips are mounted.

8. The chip on film package as claimed in claim 1, wherein a number of the one or more first chips are plural.

9. The chip on film package as claimed in claim 8, wherein the first chips are mounted on the first surface in a side-by-side manner.

10. The chip on film package as claimed in claim 1, wherein a number of the one or more second chips are plural.

11. The chip on film package as claimed in claim 10, wherein the second chips are mounted on the second surface in a side-by-side manner.

12. The chip on film package as claimed in claim 1, further comprising a substrate connected to a peripheral region of the flexible film and electrically connected to the first patterned circuit layer and/or the second patterned circuit layer.

13. The chip on film package as claimed in claim 12, wherein the substrate comprises a glass substrate or a printed circuit board.

14. The chip on film package as claimed in claim 12, wherein the flexible film further comprises a plurality of vias electrically connecting the first patterned circuit layer and the second patterned circuit layer.

15. The chip on film package as claimed in claim 1, further comprising a first substrate connected to a peripheral region of the first surface and a second substrate connected to a peripheral region of the second surface, wherein the first substrate is electrically connected to the first patterned circuit layer and the second substrate is electrically connected to the second patterned circuit layer.