Power and Temperature Management for Functional Blocks Implemented by a 3D Stacked Integrated Circuit

• US 20200135697A1
• Filed: 10/24/2018
• Published: 04/30/2020
• Est. Priority Date: 10/24/2018
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Brewer, Tony M.
• Granted Patent: US 10,748,874 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06575 Auxiliary carrier between devices, the carrier having no electrical connection structure
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

A three-dimensional stacked integrated circuit (3D SIC) having a non-volatile memory die, a volatile memory die, a logic die, and a thermal management component. The non-volatile memory die, the volatile memory die, the logic die, and the thermal management component are stacked. The thermal management component can be stacked in between the non-volatile memory die and the logic die, stacked in between the volatile memory die and the logic die, or both.

Claims

1. A three-dimensional stacked integrated circuit (3D SIC), comprising:

a non-volatile memory die;

a volatile memory die;

a logic die; and

a thermal management component having a different thermal conductivity than the dies,

wherein the non-volatile memory die, the volatile memory die, the logic die, and the thermal management component are stacked,

wherein the thermal management component is stacked in between the non-volatile memory die and the logic die or stacked in between the volatile memory die and the logic die, and

wherein the non-volatile memory die, the volatile memory die, and the logic die are arranged to form an array of functional blocks.

2. The 3D SIC of claim 1, further comprising an electrical temperature sensor located in between the thermal management component and the logic die, wherein the electrical temperature sensor is configured to measure a temperature of either a part of the logic die, a part of the thermal management component, or a heat exchange medium in between the thermal management component and the logic die, and wherein the sensor is configured to communicate the measured temperature to one of the memory dies.

3. The 3D SIC of claim 2, wherein the volatile memory die is configured to store the measured temperature.

4. The 3D SIC of claim 3, wherein the logic die is configured to:

identify whether the stored temperature exceeds a predetermined threshold; and

reduce usage of the 3D SIC, in response to identifying that the stored temperature exceeds the predetermined threshold.

5. The 3D SIC of claim 4, wherein the logic die is configured to change usage of the 3D SIC from reduced usage to normal usage, in response to identifying that the stored temperature does not exceed the predetermined threshold.

6. The 3D SIC of claim 1, wherein:

at least two functional blocks of the array of functional blocks each comprises a different data processing function; and

each functional block of the array of functional blocks comprises a respective column of the 3D SIC.

7. The 3D SIC of claim 6, wherein the respective column comprises:

a respective non-volatile memory partition of an array of non-volatile memory partitions of the non-volatile memory die, wherein each partition of the array of non-volatile memory partitions comprises an array of non-volatile memory cells;

a respective volatile memory partition of an array of volatile memory partitions of the volatile memory die, wherein each partition of the array of volatile memory partitions comprises an array of volatile memory cells;

a respective logic partition of an array of logic partitions of the logic die; and

a respective thermal management partition of an array of thermal management partitions of the thermal management component.

8. The 3D SIC of claim 7, wherein:

the respective logic partition is stacked in between the respective non-volatile memory partition and the respective volatile memory partition; and

the respective thermal management partition is stacked in between the respective non-volatile memory partition and the respective logic partition and/or stacked in between the respective volatile memory partition and the respective logic partition.

9. The 3D SIC of claim 7, further comprising an array of electrical temperature sensors.

10. The 3D SIC of claim 9, wherein each sensor of the array of electrical temperature sensors is coupled to a respective through silicon via (TSV) by a communicative coupling between the TSV and the electrical temperature sensor.

11. The 3D SIC of claim 9, wherein the respective column of the 3D SIC comprises a respective electrical temperature sensor of the array of electrical temperature sensors, and wherein the respective electrical temperature sensor is stacked in between the respective thermal management partition and the respective logic partition.

12. The 3D SIC of claim 11, wherein the respective electrical temperature sensor is configured to measure a respective temperature of the respective logic partition, the respective thermal management partition, or a heat exchange medium in between the respective thermal management partition and the respective logic partition, and wherein the respective electrical temperature sensor is configured to communicate the measured respective temperature to a memory partition of one of the memory dies.

13. The 3D SIC of claim 12, further comprising:

a port configured to communicatively couple the respective volatile memory partition to a bus,

wherein the volatile memory die is configured to;

store the measured respective temperature in the respective volatile memory partition;

receive, from the bus through the port, a request of a controller that is configured to instruct the 3D SIC to retrieve the measured respective temperature from the respective volatile memory partition; and

in response to receiving the request, communicate, via the port, the stored respective temperature to the bus according to the request.

14. The 3D SIC of claim 13, wherein the controller is configured to:

identify whether the stored respective temperature exceeds a predetermined threshold, in response to receiving the stored respective temperature via the bus; and

reduce usage of the 3D SIC, in response to identifying that the stored respective temperature exceeds the predetermined threshold.

15. The 3D SIC of claim 1, further comprising a plurality of through silicon vias (TSVs) that interconnect the logic die, the non-volatile memory die, and the volatile memory die and that run through the dies and the thermal management component.

16. The 3D SIC of claim 1, further comprising:

a plurality of through silicon vias (TSVs) that interconnect the logic die, the non-volatile die, and the volatile die and that run through the dies; and

a plurality of metal interconnects that run through the thermal management component and connect respective TSVs of the plurality of TSVs on opposing sides of the thermal management component.

17. The 3D SIC of claim 1, wherein the thermal management component comprises a heat spreader comprising silicon and high metal density.

18. The 3D SIC of the claim 1, further comprising a Peltier cooling plate stacked on the bottom or the top of the 3D SIC.

19. A three-dimensional stacked integrated circuit (3D SIC), comprising:

a logic die;

a 3D XPoint (3DXP) die;

a dynamic random-access memory (DRAM) die, wherein the logic die is stacked between the 3DXP die and the DRAM die;

a plurality of through silicon vias (TSVs) that interconnect the logic die, the 3DXP die, and the DRAM die and that run through the dies; and

a thermal management component that is stacked in between the 3DXP die and the logic die or stacked in between the DRAM die and the logic die, and wherein the thermal management component has a different thermal conductivity than the dies, wherein the 3DXP die, the DRAM die, and the logic die are arranged to form an array of functional blocks.

20. A three-dimensional stacked integrated circuit (3D SIC), comprising:

a 3D XPoint (3DXP) die comprising an array of non-volatile memory partitions, wherein each partition of the array of non-volatile memory partitions comprises an array of non-volatile memory cells;

a volatile memory die comprising an array of volatile memory partitions, wherein each partition of the array of volatile memory partitions comprises an array of volatile memory cells;

a logic die comprising an array of logic partitions, wherein the 3DXP die, the volatile memory die, and the logic die are stacked;

a through silicon via (TSV) that connects and runs through a respective non-volatile memory partition, a respective logic partition, and a respective volatile partition in a respective column of the 3D SIC; and

a thermal management component that is stacked in between the 3DXP die and the logic die and/or stacked in between the volatile memory die and the logic die, and wherein the thermal management component has a different thermal conductivity than the dies.