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Power and Temperature Management for Functional Blocks Implemented by a 3D Stacked Integrated Circuit

  • US 20200135697A1
  • Filed: 10/24/2018
  • Published: 04/30/2020
  • Est. Priority Date: 10/24/2018
  • Status: Active Grant
First Claim
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1. A three-dimensional stacked integrated circuit (3D SIC), comprising:

  • a non-volatile memory die;

    a volatile memory die;

    a logic die; and

    a thermal management component having a different thermal conductivity than the dies,wherein the non-volatile memory die, the volatile memory die, the logic die, and the thermal management component are stacked,wherein the thermal management component is stacked in between the non-volatile memory die and the logic die or stacked in between the volatile memory die and the logic die, andwherein the non-volatile memory die, the volatile memory die, and the logic die are arranged to form an array of functional blocks.

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