DIE STACK STRUCTURE, SEMICONDUCTOR PACKAGE HAVING THE SAME AND METHOD OF MANUFACTURING THE SAME

• US 20200135698A1
• Filed: 08/06/2019
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: HONG, Ji-Seok, KIM, Ji-Hoon, KIM, Tae-Hun, LEE, Hyuek-Jae, HWANG, Ji-Hwan
• Granted Patent: US 10,886,255 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/08 of an individual bonding area
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73251 on different surfaces
• CPC Class Codes: H01L 2224/80 Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 2224/80203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/92125 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3135 : Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/3142 : Sealing arrangements between parts, e.g. adhesion promotors
• CPC Class Codes: H01L 23/3185 : the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5386 : Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/18301 : being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

A die stack structure may include a base die having base contact pads insulated by a base protection patterns and a flat side surface, a die stack bonded to the base die and having a plurality of component dies on the base die such that each of the component dies includes component contact pads insulated by a corresponding component protection pattern, and a residual mold unevenly arranged on a side surface of the die stack such that the component dies are attached to each other by the residual mold.

Claims

1. A die stack structure comprising:

a base die having a base contact pad insulated by a base protection pattern, the base die having a flat side surface;

a die stack directly bonded to the base die and having a plurality of component dies, each of the component dies including a component contact pad insulated by a component protection pattern; and

a residual mold unevenly arranged on a side surface of the die stack.

2. The die stack structure of claim 1, wherein the die stack includes a plurality of the component dies having substantially the same width and side surfaces of the component dies are vertically aligned with one another.

3. The die stack structure of claim 2, wherein the residual mold is continuous along the side surface of the die stack.

4. The die stack structure of claim 2, wherein the residual mold is discontinuous along the side surface of the die stack.

5. The die stack structure of claim 1, wherein the base die and the die stack are directly bonded to each other by a hybrid bonding structure in which the base contact pad and the component contact pad of the lowermost component die of the die stack are mutually adjacent and bonded to each other and the base protection pattern and the component protection pattern of the lowermost component die are mutually adjacent and bonded to each other.

6. The die stack structure of claim 5, wherein a width of the base die is greater than a width of the lowermost component die of the die stack.

7. The die stack structure of claim 5, wherein the base contact pad and the component contact pad of the lowermost component die include the same material which is one of copper (Cu), aluminum (Al) and lead (Pb), and the base protection pattern and the component protection pattern of the lowermost component die include the same material which is one of silicon oxide, silicon nitride and silicon oxynitride.

8. The die stack structure of claim 5, wherein neighboring ones of the component dies are directly bonded to each other by a hybrid bonding structure in which neighboring component contact pads contact each other and neighboring component protection patterns contact each other.

9. The die stack structure of claim 1, further comprising a base penetration electrode in contact with the base contact pad and penetrating through the base die and a component penetration electrode in contact with the component contact pad of the lowermost component die of the die stack and penetrating through the lower most component die.

10. A semiconductor package comprising:

a package substrate comprising a circuit board having an electronic circuit pattern;

a die stack structure comprising a stack of semiconductor dies, the die stack structure being arranged on the circuit board such that the die stack structure is connected to the electronic circuit pattern; and

a package mold securing the die stack structure to the circuit board,

wherein the die stack structure includes;

a base die connected to the electronic circuit pattern and having base contact pads insulated by base protection patterns and a flat side surface;

a die stack directly bonded to the base die and having a plurality of component dies on the base die, each component die including component contact pads insulated by component protection patterns; and

a residual mold unevenly arranged on a side surface of the die stack.

11. The semiconductor package of claim 10,

wherein the die stack includes a plurality of the component dies having substantially the same footprint, and

wherein side surfaces of the component dies are vertically arranged.

12. The semiconductor package of claim 10, wherein the base die and the die stack are directly bonded to each other by a hybrid bonding structure in which the base contact pads and adjacent component contact pads of the lowermost component die of the die stack are bonded to each other and the base protection patterns and adjacent component protection patterns of the lower most component die are bonded to each other.

13. The semiconductor package of claim 12, wherein neighboring ones of the component dies are directly bonded to each other by a hybrid bonding structure in which neighboring component contact pads are bonded to each other and neighboring component protection patterns are bonded to each other.

14. The semiconductor package of claim 10, wherein the die stack structure further includes base penetration electrodes in contact with corresponding ones of the base contact pads and penetrating through the base die and component penetration electrodes in contact with corresponding ones of the component contact pads and penetrating through a corresponding component die.

15. The semiconductor package of claim 14, further comprising contact terminals in contact with corresponding base contact pads and the electronic circuit pattern such that the electronic circuit pattern electrically connects with the base penetration electrodes.

16. The semiconductor package of claim 15, further comprising an under fill mold interposed between the package substrate and the die stack structure.

17. The semiconductor package of claim 10, wherein the residual mold is continuous along the side surface of the die stack.

18. The semiconductor package of claim 10, wherein the residual mold is discontinuous along the side surface of the die stack.

19. The semiconductor package of claim 10, wherein a width of the base die is greater than a width of the die stack.

20. The semiconductor package of claim 10, wherein the base die and the component dies includes one of a dynamic random access memory (DRAM) device and a flash memory device.

21-27. -27. (canceled)