SEMICONDUCTOR PACKAGE

• US 20200135699A1
• Filed: 10/01/2019
• Published: 04/30/2020
• Est. Priority Date: 10/24/2018
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: HWANG, Ji Hwan, KIM, Ji Hoon, HONG, Ji Seok, KIM, Tae Hun, LEE, Hyuek Jae
• Granted Patent: US 11,145,626 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/08 of an individual bonding area
• CPC Class Codes: H01L 2224/08058 being non uniform along the bonding area
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/08146 the bonding area connecting to a via connection in the body
• CPC Class Codes: H01L 2224/08237 the bonding area connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/09181 On opposite sides of the body
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/29194 with a principal constituent of the material being a liquid not provided for in groups H01L2224/291 - H01L2224/29191
• CPC Class Codes: H01L 2224/2929 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/29299 Base material
• CPC Class Codes: H01L 2224/32 of an individual layer connector
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73251 on different surfaces
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 2224/80203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/8034 : Bonding interfaces of the bonding area
• CPC Class Codes: H01L 2224/8083 : Solid-solid interdiffusion
• CPC Class Codes: H01L 2224/80895 : between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/80896 : between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/9202 : Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06586 : Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/36 : Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/09 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0665 : Epoxy resin

Abstract

A semiconductor package includes a base structure having a base pad, a first semiconductor chip on the base structure, and having a first connection pad bonded to the base pad, a first bonding structure including an base insulation layer of a base structure and a first lower insulation layer of the first semiconductor chip bonded to the base insulation layer, a second semiconductor chip on the first semiconductor chip, and having a second connection pad connected to the first through-electrode, and a second bonding structure including a first upper insulation layer of the first semiconductor chip, and a second lower insulation layer of the second semiconductor chip bonded to the first upper insulation layer, and the first upper insulation layer has a dummy insulation portion extending onto the base structure around the first semiconductor chip.

Claims

1. A semiconductor package, comprising:

a base structure having a lower surface and an upper surface, and having a first pad on the lower surface, and a second pad on the upper surface;

a first semiconductor chip stacked on the upper surface of the base structure, and having a first connection pad directly bonded to the second pad and a first through-electrode connected to the first connection pad;

a first bonding structure disposed between the base structure and the first semiconductor chip, the first bonding structure including an base insulation layer on the upper surface of the base structure, and a first lower insulation layer on the first semiconductor chip, the first lower insulation layer directly bonded to the base insulation layer;

a second semiconductor chip stacked on the first semiconductor chip, and having a second connection pad connected to the first through-electrode; and

a second bonding structure disposed between the first semiconductor chip and the second semiconductor chip, the second bonding structure including a first upper insulation layer on the first semiconductor chip, and a second lower insulation layer on the second semiconductor chip, the second lower insulation layer directly bonded to the first upper insulation layer,

wherein the first upper insulation layer has a dummy insulation portion extending onto the base structure around the first semiconductor chip.

2. The semiconductor package as claimed in claim 1, wherein:

the first semiconductor chip includes a first bonding pad connected to the first through-electrode and embedded in the first upper insulation layer, and

the second connection pad is directly bonded to the first bonding pad.

3. The semiconductor package as claimed in claim 1, wherein:

the first through-electrode has an exposed portion at an upper surface of the first upper insulation layer, and

the second connection pad is directly bonded to the exposed portion of the first through-electrode.

4. The semiconductor package as claimed in claim 1, further comprising a molding member surrounding the first and second semiconductor chips on the base structure.

5. The semiconductor package as claimed in claim 4, wherein the molding member has a resin portion disposed around the first semiconductor chip on the base structure, and wherein the dummy insulation portion is disposed on the resin portion.

6. The semiconductor package as claimed in claim 5, wherein the resin portion has an upper surface substantially coplanar with an upper surface of the first semiconductor chip.

7. The semiconductor package as claimed in claim 6, wherein the dummy insulation portion has substantially the same thickness as that of the upper insulation layer of the first semiconductor chip.

8. The semiconductor package as claimed in claim 4, wherein the molding member is disposed on the dummy insulation portion.

9. The semiconductor package as claimed in claim 4, further comprising a heat dissipating plate on the second semiconductor chip surrounded by the molding member.

10. A semiconductor package, comprising:

a base structure having a lower surface and an upper surface, and having a first pad on the lower surface, and a second pad and a base insulation layer on the upper surface;

a first semiconductor chip stacked on the upper surface of the base structure, having a lower surface and an upper surface, and having a first connection pad and a first lower insulation layer on the lower surface, a first bonding pad and a first upper insulation layer on the upper surface, and a first through-electrode connected to the first connection pad and first bonding pad, the first connection pad directly bonded to the second pad, and the first lower insulation layer directly bonded to the base insulation layer;

at least one second semiconductor chip stacked on the upper surface of the first semiconductor chip, having a lower surface and an upper surface, and having a second connection pad and a second lower insulation layer on the lower surface, a second bonding pad and a second upper insulation layer on the upper surface, and a second through-electrode connected to the second connection pad and second bonding pad, the second connection pad directly bonded to the first bonding pad, and the second lower insulation layer directly bonded to the first upper insulation layer;

a third semiconductor chip stacked on the upper surface of the second semiconductor chip, having a lower surface and an upper surface, and having a third connection pad and a third lower insulation layer on the lower surface, the third connection pad directly bonded to the second bonding pad, and the third lower insulation layer directly bonded to the second upper insulation layer;

a first dummy insulation portion on the base structure around the first semiconductor chip and extending from the first upper insulation layer overlapping with the second semiconductor chip; and

a second dummy insulation portion on first dummy insulation portion and extending from the second upper insulation layer overlapping with the third semiconductor chip.

11. The semiconductor package as claimed in claim 10, further comprising a molding member surrounding the first, the second and the third semiconductor chips on the base structure.

12. The semiconductor package as claimed in claim 11, wherein the molding member has a first resin portion around the first semiconductor chip, the second resin portion around the second semiconductor chip and the third resin portion around the third semiconductor chip, and

the first dummy insulation portion is disposed between the first resin portion and the second resin portion, and the second dummy insulation portion is disposed between the second resin portion and the third resin portion.

13. The semiconductor package as claimed in claim 12, wherein the first resin portion has an upper surface substantially coplanar with the upper surface of the first semiconductor chip, and wherein the second resin portion has an upper surface substantially coplanar with the upper surface of the second semiconductor chip.

14. The semiconductor package as claimed in claim 11, wherein the first dummy insulation portion is disposed on the base insulation layer and a side surface of the first semiconductor chip;

and the second dummy insulation portion is disposed on first dummy insulation portion and a side surface of the second semiconductor chip.

15. The semiconductor package as claimed in claim 10, wherein a width of the base structure is larger than that of the first semiconductor chip.

16. A semiconductor package, comprising:

a base structure having a lower surface and an upper surface, and having a first pad on the lower surface, and a second pad and a base insulation layer on the upper surface;

a first semiconductor chip stacked on the upper surface of the base structure, having a lower surface and an upper surface, and having a first connection pad and a first lower insulation layer on the lower surface, a first upper insulation layer on the upper surface, and a first through-electrode connected to the first connection pad and exposed from the first upper insulation layer, the first connection pad directly bonded to the second pad, and the first lower insulation layer directly bonded to the base insulation layer;

at least one second semiconductor chip stacked on the upper surface of the first semiconductor chip, having a lower surface and an upper surface, and having a second connection pad and a second lower insulation layer on the lower surface, a second upper insulation layer on the upper surface, and a second through-electrode connected to the second connection pad and exposed from the second upper insulation layer, the second connection pad directly bonded to the first through-electrode, and the second lower insulation layer directly bonded to the first upper insulation layer;

a third semiconductor chip stacked on the upper surface of the second semiconductor chip, having a lower surface and an upper surface, and having a third connection pad and a third lower insulation layer on the lower surface, the third connection pad directly bonded to the second through-electrode, and the third lower insulation layer directly bonded to the second upper insulation layer;

a first dummy insulation portion on the base structure around the first semiconductor chip and extending from the first upper insulation layer vertically overlapping with the second semiconductor chip; and

a second dummy insulation portion on first dummy insulation portion and extending from the second upper insulation layer vertically overlapping with the third semiconductor chip.

17. The semiconductor package as claimed in claim 16, further comprising a molding member surrounding the first, the second and the third semiconductor chips on the base structure.

18. The semiconductor package as claimed in claim 17, wherein the molding member has a first resin portion around the first semiconductor chip, the second resin portion around the second semiconductor chip and the third resin portion around the third semiconductor chip, and

the first dummy insulation portion is disposed between the first resin portion and the second resin portion, and the second dummy insulation portion is disposed between the second resin portion and the third resin portion.

19. The semiconductor package as claimed in claim 18, wherein the first resin portion has an upper surface substantially coplanar with the upper surface of the first semiconductor chip, and wherein the second resin portion has an upper surface substantially coplanar with the upper surface of the second semiconductor chip.

20. The semiconductor package as claimed in claim 17, wherein the first dummy insulation portion is disposed on the base insulation layer and a side surface of the first semiconductor chip, the second dummy insulation portion is disposed on first dummy insulation portion and a side surface of the second semiconductor chip, and the molding member is disposed on the second dummy insulation portion.