MULTI-CHIP MODULE HAVING A STACKED LOGIC CHIP AND MEMORY STACK

• US 20200135700A1
• Filed: 12/26/2019
• Published: 04/30/2020
• Est. Priority Date: 12/26/2019
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: SHARMA, Abhishek, YOO, Hui Jae, LE, Van H., SUMBUL, Huseyin Ekin, KNAG, Phil, CHEN, Gregory K., KRISHNAMURTHY, Ram
• Granted Patent: US 11,699,681 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/08146 the bonding area connecting to a via connection in the body
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/24146 the HDI interconnect connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/9212 Sequential connecting processes
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 24/08 of an individual bonding area
• CPC Class Codes: H01L 24/80 Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys

Abstract

An apparatus is formed. The apparatus includes a stack of semiconductor chips. The stack of semiconductor chips includes a logic chip and a memory stack, wherein, the logic chip includes at least one of a GPU and CPU. The apparatus also includes a semiconductor chip substrate. The stack of semiconductor chips are mounted on the semiconductor chip substrate. At least one other logic chip is mounted on the semiconductor chip substrate. The semiconductor chip substrate includes wiring to interconnect the stack of semiconductor chips to the at least one other logic chip.

Claims

1. An apparatus, comprising:

a stack of semiconductor chips, the stack of semiconductor chips comprising a logic chip and a memory stack, wherein, the logic chip comprises at least one of a GPU and CPU; and

a semiconductor chip substrate, the stack of semiconductor chips mounted on the semiconductor chip substrate, at least one other logic chip mounted on the semiconductor chip substrate, the semiconductor chip substrate comprising wiring to interconnect the stack of semiconductor chips to the at least one other logic chip.

2. The apparatus of claim 1 wherein the memory stack is between the semiconductor chip substrate and the logic chip.

3. The apparatus of claim 2 wherein a back of a top memory chip of the memory stack interfaces with a face of the logic chip.

4. The apparatus of claim 3 wherein a substrate of the logic chip comprises a through silicon via.

5. The apparatus of claim 2 wherein a face of a top memory chip of the memory stack interfaces with a face of the logic chip.

6. The apparatus of claim 5 wherein a substrate of the logic chip comprises a through silicon via.

7. The apparatus of claim 2 wherein power is provided to the logic chip at a top surface of the logic chip.

8. The apparatus of claim 1 wherein the logic chip is between the semiconductor chip substrate and the memory stack.

9. The apparatus of claim 8 wherein a back of the logic chip interfaces with a face of a bottom memory chip of the memory stack.

10. The apparatus of claim 9 wherein a substrate of the bottom memory chip of the memory stack comprises a through silicon via.

11. The apparatus of claim 8 wherein a face of the logic chip interfaces with a face of a bottom memory chip of the memory stack.

12. The apparatus of claim 11 wherein a substrate of a bottom memory chip of the memory stack comprises a through silicon via.

13. The apparatus of claim 8 wherein power is provided to the memory stack at a top surface of the memory stack.

14. A computing system, comprising:

a networking interface;

non volatile mass storage; and

a multi-chip module comprising a) and b) below;

a) a stack of semiconductor chips, the stack of semiconductor chips comprising a logic chip and a memory stack, wherein, the logic chip comprises at least one of a GPU and CPU;

b) a semiconductor chip substrate, the stack of semiconductor chips mounted on the semiconductor chip substrate, at least one other logic chip mounted on the semiconductor chip substrate, the semiconductor chip substrate comprising wiring to interconnect the stack of semiconductor chips to the at least one other logic chip.

15. The computing system of claim 14 wherein the memory stack is between the semiconductor chip substrate and the logic chip.

16. The computing system of claim 15 wherein power is provided to the logic chip at a top surface of the logic chip.

17. The computing system of claim 14 wherein the logic chip is between the semiconductor chip substrate and the memory stack.

18. The computing system of claim 17 wherein power is provided to the memory stack at a top surface of the memory stack.

19. The computing system of claim 15 wherein power is provided to at least one of the memory stack and the logic chip through the semiconductor chip substrate.

20. A method, comprising:

stacking multiple memory chip wafers and a logic chip wafer;

dicing the stacked memory chip wafers and logic chip wafer to form a stacked logic chip and memory stack;

mounting the stacked logic chip and memory stack on a semiconductor chip substrate; and

,

mounting at least one other logic chip to the semiconductor chip substrate.