PACKAGE STRUCTURE, DIE AND METHOD OF MANUFACTURING THE SAME

• US 20200135708A1
• Filed: 01/29/2019
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Wei-Yu, Su, An-Jhih, Yeh, Der-Chyang, Tseng, Hua-Wei, Huang, Li-Hsien, Yeh, Ming-Shih
• Granted Patent: US 10,879,224 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76871 Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02373 Layout of the redistribution layers
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/214 Connecting portions
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/24195 the item being a discrete passive component
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5226 : Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5383 : Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5386 : Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/09 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/33 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA

Abstract

A package structure, a die and method of forming the same are provided. The package structure includes a die, an encapsulant, a RDL structure, and a conductive terminal. The die has a connector. The connector includes a seed layer and a conductive on the seed layer. The seed layer extends beyond a sidewall of the conductive pillar. The encapsulant is aside the die and encapsulates sidewalls of the die. The RDL structure is electrically connected to the die. The conductive terminal is electrically connected to the die through the RDL structure.

Claims

1. A package structure, comprising:

a die having a connector, the connector comprising;

a seed layer; and

a conductive pillar on the seed layer, wherein the seed layer extends beyond a sidewall of the conductive pillar;

an encapsulant aside the die, encapsulating sidewalls of the die;

a redistribution layer (RDL) structure, electrically connected to the die; and

a conductive terminal, electrically connected to the die through the RDL structure.

2. The package structure of claim 1, wherein the seed layer comprises a footing portion, and the footing portion is laterally protruding from the sidewall of the conductive pillar.

3. The package structure of claim 2, wherein the die further comprises a protection layer laterally surrounding the connector, a top surface and a sidewall of the footing portion being covered by the protection layer of the die.

4. The package structure of claim 3, wherein the footing portion is located between a passivation layer of the die and the protection layer.

5. The package structure of claim 2, wherein a top surface and a sidewall of the footing portion is covered by the encapsulant.

6. The package structure of claim 5, wherein the footing portion is located between a passivation layer of the die and the encapsulant.

7. The package structure of claim 1, wherein a width of the seed layer is larger than a width of the conductive pillar.

8. The package structure of claim 1, wherein the connector is electrically connected to two pads of the die.

9. The package structure of claim 1, wherein the seed layer comprises a first seed sublayer and a second seed sublayer on the first seed sublayer, and an edge of the seed layer comprises a stepped structure.

10. The package structure of claim 9, wherein a sidewall of the first seed sublayer is more distant from a center line of the connector than a sidewall of the second seed layer is from the center line of the connector.

11. A die, comprising:

a substrate;

a pad over the substrate; and

a connector, electrically connected to the pad, comprising;

a seed layer on the pad; and

a conductive pillar on the seed layer,

wherein the seed layer comprises a footing portion, and a projection of the footing portion on a top surface of the substrate surrounds a projection of the conductive pillar on the top surface of the substrate.

12. The die of claim 11, wherein the footing portion of the seed layer is exposed by the conductive pillar.

13. The die of claim 11, wherein a sidewall of the footing portion is more distant from a center line of the connector than a sidewall of the conductive pillar from the center line of the connector in a horizontal direction.

14. The die of claim 11, further comprising a protection layer over the substrate and covering sidewalls of the connector, wherein the protection layer comprises low temperature polyimide (PI) or high temperature polybenzoxazole (PBO).

15. A method of forming a package structure, comprising:

forming a die, comprising;

forming a connector on and electrically connected to a pad, comprising;

forming a seed layer on the pad;

forming a conductive pillar on the seed layer;

forming a test pad on the conductive pillar;

performing an electrical testing through the test pad; and

performing an etching process to remove the test pad, wherein the conductive pillar is consumed during the etching process, such that a footing portion of the seed layer laterally protrudes from a sidewall of the conductive pillar;

forming an encapsulant aside the die to encapsulate sidewalls of the die;

forming a redistributuion (RDL) structure on the die and the encapsulant; and

forming a conductive terminal, electrically connected to the die through the RDL structure.

16. The method of claim 15, wherein during the etching process, an etching selectivity ratio of the test pad to the conductive pillar is less than an etching selectivity ratio of the test pad to the seed layer.

17. The method of claim 15, wherein an etchant used in the etching process comprises an H₂SO₄ based etchant, an HNO₃ based etchant, or a combination thereof.

18. The method of claim 15, wherein the conducive pillar is consumed from a sidewall during the etching process.

19. The method of claim 15, wherein

before performing the etching process, a first width of the seed layer is less than a first width of the conductive pillar;

and

after performing the etching process, a second width of the seed layer is larger than a second width of the conductive pillar.

20. The method of claim 16, wherein after performing the etching process, a footing portion of the seed layer extends beyond a sidewall of the conductive pillar.