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SOLENOID INDUCTORS WITHIN A MULTI-CHIP PACKAGE

  • US 20200135709A1
  • Filed: 02/22/2019
  • Published: 04/30/2020
  • Est. Priority Date: 10/31/2018
  • Status: Active Grant
First Claim
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1. A multi-chip package, comprising:

  • an enclosed integrated circuit (IC) package comprising;

    a first plurality of conductive layers disposed onto a semiconductor substrate, the first plurality of conductive layers including a first portion of a first solenoid inductor and a first portion of a second solenoid inductor,wherein the semiconductor substrate comprises;

    a plurality of through silicon via (TSV) structures to electrically couple the first portion of the first solenoid inductor and a second portion of the first solenoid inductor; and

    an enclosing IC package comprising;

    a plurality of system on chip (SoC) packages,a first interposer, situated onto the plurality of SoC packages, having a second plurality of conductive layers, wherein a second portion of the second solenoid inductor and a first portion of a third solenoid inductor are situated within the second plurality of conductive layers,a second interposer, situated onto the enclosed IC package, having a third plurality of conductive layers, wherein the second portion of the first solenoid inductor and a second portion of a third solenoid inductor are situated within the third plurality of conductive layers,a plurality of regions of a molding compound situated between the first interposer and the second interposer, wherein the plurality of regions of the molding compound include a plurality via structures to electrically couple the first portion of the third solenoid inductor and the second portion of the third solenoid inductor, anda plurality of regions of conductive material situated between the enclosed IC package and the first interposer to electrically couple the first portion of the second solenoid inductor and the second portion of the second solenoid inductor.

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