SOLENOID INDUCTORS WITHIN A MULTI-CHIP PACKAGE

• US 20200135709A1
• Filed: 02/22/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: LEE, Hui Yu, CHANG, Ka Fai
• Granted Patent: US 10,971,485 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/32058 being non uniform along the layer connector
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73259 Bump and HDI connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/92224 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5227 : Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5383 : Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5385 : Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/645 : Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 23/66 : High-frequency adaptations
• CPC Class Codes: H01L 24/04 : Structure, shape, material or disposition of the bonding areas prior to the connecting process
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect

Abstract

An exemplary multi-chip package includes one or more solenoid inductors. An exemplary enclosing IC package includes one or more electrical interconnections propagating throughout which can be arranged to form a first solenoid inductor situated within the exemplary multi-chip package. Moreover, the exemplary enclosing IC package can be connected to an exemplary enclosed IC package to form the exemplary multi-chip package. The exemplary enclosed IC package can include a second solenoid inductor formed therein. Furthermore, the exemplary enclosing IC package can include a first portion of a third solenoid inductor and the exemplary enclosed IC package can include a second portion of the third solenoid inductor. The exemplary enclosed IC package can be connected to the exemplary enclosing IC package to connect the first portion of the third solenoid inductor and the second portion of the third solenoid inductor to form the third solenoid inductor.

Claims

1. A multi-chip package, comprising:

an enclosed integrated circuit (IC) package comprising;

a first plurality of conductive layers disposed onto a semiconductor substrate, the first plurality of conductive layers including a first portion of a first solenoid inductor and a first portion of a second solenoid inductor,

wherein the semiconductor substrate comprises;

a plurality of through silicon via (TSV) structures to electrically couple the first portion of the first solenoid inductor and a second portion of the first solenoid inductor; and

an enclosing IC package comprising;

a plurality of system on chip (SoC) packages,

a first interposer, situated onto the plurality of SoC packages, having a second plurality of conductive layers, wherein a second portion of the second solenoid inductor and a first portion of a third solenoid inductor are situated within the second plurality of conductive layers,

a second interposer, situated onto the enclosed IC package, having a third plurality of conductive layers, wherein the second portion of the first solenoid inductor and a second portion of a third solenoid inductor are situated within the third plurality of conductive layers,

a plurality of regions of a molding compound situated between the first interposer and the second interposer, wherein the plurality of regions of the molding compound include a plurality via structures to electrically couple the first portion of the third solenoid inductor and the second portion of the third solenoid inductor, and

a plurality of regions of conductive material situated between the enclosed IC package and the first interposer to electrically couple the first portion of the second solenoid inductor and the second portion of the second solenoid inductor.

2. The multi-chip package of claim 1, wherein the enclosing IC package further comprises:

a non-conductive platform situated onto the first interposer to mechanically connect the enclosed IC package and the first interposer, the non-conductive platform including the plurality of regions of conductive material.

3. The multi-chip package of claim 1, wherein the first solenoid inductor comprises:

a first three-dimensional structure of conductive material having first turns rotating in a counter-clockwise direction between an input of the first solenoid inductor and an output of the first solenoid inductor,

wherein the second solenoid inductor comprises;

a second three-dimensional structure of the conductive material having second turns rotating in the counter-clockwise direction between an input of the second solenoid inductor and an output of the second solenoid inductor, and

wherein the third solenoid inductor comprises;

a third three-dimensional structure of the conductive material having third turns rotating in the counter-clockwise direction between an input of the third solenoid inductor and an output of the third solenoid inductor.

4. The multi-chip package of claim 3, wherein the first solenoid inductor is arranged to traverse a first current there through to generate a first magnetic field, and

wherein the second solenoid inductor is arranged to traverse a second current there through to generate a second magnetic field.

5. The multi-chip package of claim 4, wherein the first solenoid inductor is arranged to traverse the first current there through in the counter-clockwise direction between the input of the first solenoid inductor and the output of the first solenoid inductor to generate the first magnetic field, and

wherein the second solenoid inductor is arranged to traverse the first current there through in the counter-clockwise direction to generate the second magnetic field,

wherein the first magnetic field and the second magnetic field are constructive to increase an inductance of the third solenoid inductor.

6. The multi-chip package of claim 4, wherein the first solenoid inductor is arranged to traverse the first current there through in a clockwise direction between the output of the first solenoid inductor and the input of the first solenoid inductor to generate the first magnetic field, and

wherein the second solenoid inductor is arranged to traverse the first current there through in the counter-clockwise direction between the input of the second solenoid inductor and the output of the second solenoid inductor to generate the second magnetic field,

wherein the first magnetic field and the second magnetic field are destructive to decrease an inductance of the third solenoid inductor.

7. The multi-chip package of claim 4, wherein an inductance of the third solenoid inductor is related to the first magnetic field and the second magnetic field.

8. The multi-chip package of claim 1, wherein at least one of the SoC packages comprises:

a dynamic inductance control circuit configured to generate a control current to be applied to the first solenoid inductor or the second solenoid inductor, and

wherein the control current is adjustable to control an inductance of the third solenoid inductor.

9. The multi-chip package of claim 1, wherein the first solenoid inductor and the second solenoid inductor are arranged to situated within the third solenoid inductor.

10. An enclosed IC package, comprising:

a semiconductor substrate; and

a first plurality of conductive layers disposed onto the semiconductor substrate, the first plurality of conductive layers including a first portion of a first solenoid inductor and a first portion of a second solenoid inductor,

wherein the semiconductor substrate comprises;

a plurality of through silicon via (TSV) structures electrically coupled to the first portion of the first solenoid inductor.

11. The enclosed IC package of claim 10, wherein the enclosed IC package is configured to be electrically and mechanically coupled to an enclosing IC package to form a multi-chip package, the enclosing IC package comprising:

a plurality of system on chip (SoC) packages,

a first interposer, situated onto the plurality of SoC packages, having a second plurality of conductive layers, wherein a second portion of the second solenoid inductor and a first portion of a third solenoid inductor are situated within the second plurality of conductive layers,

a second interposer, situated onto the enclosed IC package, having a third plurality of conductive layers, wherein the second portion of the first solenoid inductor and a second portion of a third solenoid inductor are situated within the third plurality of conductive layers,

a plurality of regions of a molding compound situated between the first interposer and the second interposer, wherein the plurality of regions of the molding compound include a plurality via structures to electrically couple the first portion of the third solenoid inductor and the second portion of the third solenoid inductor, and

a plurality of regions of conductive material situated between the enclosed IC package and the first interposer to electrically couple the first portion of the second solenoid inductor and the second portion of the second solenoid inductor.

12. The enclosed IC package of claim 11, wherein the first portion of the first solenoid inductor is electrically coupled to the second portion of the first solenoid inductor to form the first solenoid inductor and the first portion of the second solenoid inductor is electrically coupled to the second portion of the second solenoid inductor to form the second solenoid inductor when the enclosed IC package is mechanically and electrically connected to the enclosing IC package.

13. The enclosed IC package of claim 12, wherein the first solenoid inductor is arranged to traverse a first current there through to generate a first magnetic field, and

wherein the second solenoid inductor is arranged to traverse a second current there through to generate a second magnetic field.

14. The enclosed IC package of claim 13, wherein the first solenoid inductor is arranged to traverse the first current there through in a counter-clockwise direction between an input of the first solenoid inductor and an output of the first solenoid inductor to generate the first magnetic field, and

wherein the second solenoid inductor is arranged to traverse the first current there through in the counter-clockwise direction between an input of the second solenoid inductor and an output of the second solenoid inductor to generate the second magnetic field,

wherein the first magnetic field and the second magnetic field are constructive to increase an inductance of the third solenoid inductor.

15. The enclosed IC package of claim 13, wherein the first solenoid inductor is arranged to traverse the first current there through in a clockwise direction between an output of the first solenoid inductor and an input of the first solenoid inductor to generate the first magnetic field, and

wherein the second solenoid inductor is arranged to traverse the first current there through in a counter-clockwise direction between an input of the second solenoid inductor and an output of the second solenoid inductor to generate the second magnetic field,

wherein the first magnetic field and the second magnetic field are destructive to decrease an inductance of the third solenoid inductor.

16. A method for fabricating a multi-chip package, the method comprising:

attaching at least one system on chip (SOC) on a first side of a first interposer;

forming through interpose vias (TIVs) on a second side of the first interposer opposite to the first side, wherein each of the first and second sides of the first interposer comprises a redistribution layer configured to mechanically and electrically connect, respectively, to the at least one SOC and the TIVs;

attaching an enclosed integrated circuit package to the second side of the first interposer so that a first conductive layer on a first side of the enclosed integrated circuit package is electrically coupled to a first portion of the redistribution layer on the second side of the first interposer, wherein the first conductive layer on a first side of the enclosed integrated circuit package and the first portion of the redistribution layer on the second side of the first interposer form a first solenoid inductor;

attaching a second interposer on a second side of the enclosed integrated circuit package, opposite to the first side of the enclosed integrated circuit package, so that a second conductive layer on the second side of the enclosed integrated circuit package is electrically coupled to a first portion of an redistribution layer on a first side of the second interposer and a second portion of the redistribution layer on the first side of the second interposer is electrically couple through the TIVs to a second portion of the redistribution layer on the second side of the first interposer, wherein the second conductive layer on the second side of the enclosed integrated circuit package and the first portion of the redistribution layer on the first side of the second interposer form a second solenoid inductor, and wherein the second portion of the redistribution layer on the first side of the second interposer, the TIVs, and the second portion of the redistribution layer on the second side of the first interposer form a third solenoid inductor.

17. The method of claim 16, further comprising:

forming electrical connections to a second side of the second interposer, opposite to the first side of the second interposer, so that the electrical connections are electrically coupled to the first, second, and third solenoids.

18. The method of claim 16, wherein attaching the enclosed integrated circuit package to the second side of the first interposer comprises mechanically connecting the first conductive layer on the first side of the enclosed integrated circuit package to the first portion of the redistribution layer on the second side of the first interposer through bump connections.

19. The method of claim 16, wherein attaching the second interposer on a second side of the EICP to the first portion of the redistribution layer on the first side of the second interposer comprises mechanically connecting silicon vias (TSVs) on the second side of the enclosed integrated circuit package to the first portion of the redistribution layer on the first side of the second interposer.

20. The method of claim 16, wherein attaching the enclosed integrated circuit package to the second side of the first interposer comprises forming an non-conductive platform that surrounds a portion of the first solenoid inductor.