TRENCH TRANSISTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

• US 20200135713A1
• Filed: 10/24/2018
• Published: 04/30/2020
• Est. Priority Date: 10/24/2018
• Status: Active Grant

• Current Assignee: Powerchip Semiconductor Manufacturing Corp. (Powerchip Technology Corporation)
• Original Assignee: Powerchip Semiconductor Manufacturing Corp. (Powerchip Technology Corporation)
• Inventors: Lin, Wei-Yu, Cheng, Shih-Hao
• Granted Patent: US 10,903,203 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/861 Diodes

Abstract

A trench transistor structure includes a substrate structure, a transistor device, and an electrostatic discharge (ESD) protection device. A first region and a second region are defined in the substrate structure. The substrate structure has a first trench located in the first region and a second trench located in the second region. The transistor device is located in the first region and includes an electrode located in the first trench. The electrode and the substrate structure are isolated from each other. The ESD protection device is located in the second region and includes a main body layer located in the second trench. The main body layer has a planarized top surface. PN junctions are located in the main body layer. The main body layer and the substrate structure are isolated from each other.

Claims

1. A trench transistor structure, comprising:

a substrate structure, wherein a first region and a second region are defined in the substrate structure, and the substrate structure has a first trench located in the first region and a second trench located in the second region;

a transistor device located in the first region and comprising an electrode located in the first trench, wherein the electrode and the substrate structure are isolated from each other; and

an electrostatic discharge (ESD) protection device located in the second region and comprising a main body layer located in the second trench, wherein

the main body layer has a planarized top surface,

PN junctions are located in the main body layer, and

the main body layer and the substrate structure are isolated from each other.

2. The trench transistor structure according to claim 1, wherein the main body layer fills up the second trench.

3. The trench transistor structure according to claim 1, wherein a bottom of the main body layer is higher than or equal to a bottom of the electrode.

4. The trench transistor structure according to claim 1, wherein a width of the main body layer is greater than a width of the electrode.

5. The trench transistor structure according to claim 1, wherein the substrate structure has a first conductive type.

6. The trench transistor structure according to claim 5, wherein the substrate structure comprises:

a substrate layer; and

an epitaxial layer disposed on the substrate layer.

7. The trench transistor structure according to claim 5, wherein the ESD protection device further comprises:

at least one first doped region and second doped regions alternately disposed in the main body layer to form the PN junctions, wherein the at least one first doped region has the first conductive type, and the second doped regions have a second conductive type.

8. The trench transistor structure according to claim 5, wherein the ESD protection device further comprises:

first doped regions and at least one second doped region alternately disposed in the main body layer to form the PN junctions, wherein the first doped regions have the first conductive type, and the at least one second doped region has a second conductive type.

9. The trench transistor structure according to claim 5, further comprising:

a body region located in the substrate structure at two sides of the electrode and having a second conductive type.

10. The trench transistor structure according to claim 9, wherein the transistor device further comprises:

a doped region located in the body region at one side of the electrode and having the first conductive type.

11. A method of manufacturing a trench transistor structure, comprising:

providing a substrate structure, wherein a first region and a second region are defined in the substrate structure, and the substrate structure has a first trench located in the first region and a second trench located in the second region;

forming a transistor device in the first region, wherein the transistor device comprises an electrode located in the first trench, and the electrode and the substrate structure are isolated from each other; and

forming an ESD protection device in the second region, wherein

the ESD protection device comprises a main body layer located in the second trench,

the main body layer has a planarized top surface,

PN junctions are located in the main body layer, and

the main body layer and the substrate structure are isolated from each other.

12. The method of manufacturing the trench transistor structure according to claim 11, wherein a depth of the second trench is less than or equal to a depth of the first trench.

13. The method of manufacturing the trench transistor structure according to claim 11, wherein the first trench and the second trench are separately formed.

14. The method of manufacturing the trench transistor structure according to claim 11, wherein the first trench and the second trench are simultaneously formed.

15. The method of manufacturing the trench transistor structure according to claim 11, wherein the substrate structure has a first conductive type.

16. The method of manufacturing the trench transistor structure according to claim 15, wherein a method of forming the PN junctions comprises:

forming at least one first doped region and second doped regions alternately disposed in the main body layer, wherein the at least one first doped region has the first conductive type, and the second doped regions have a second conductive type.

17. The method of manufacturing the trench transistor structure according to claim 15, wherein a method of forming the PN junctions comprises:

forming first doped regions and at least one second doped region alternately disposed in the main body layer, wherein the first doped regions have the first conductive type, and the at least one second doped region has a second conductive type.

18. The method of manufacturing the trench transistor structure according to claim 15, further comprising:

forming a body region in the substrate structure at two sides of the electrode, wherein the body region has a second conductive type.

19. The method of manufacturing the trench transistor structure according to claim 18, wherein a method of forming the transistor device comprises:

forming a doped region in the body region at one side of the electrode, wherein the doped region has the first conductive type.

20. The method of manufacturing the trench transistor structure according to claim 11, wherein the electrode and the main body layer are formed by the same material layer.