SILICON-CONTROLLED RECTIFIERS WITH WELLS LATERALLY ISOLATED BY TRENCH ISOLATION REGIONS

• US 20200135715A1
• Filed: 10/26/2018
• Published: 04/30/2020
• Est. Priority Date: 10/26/2018
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Loiseau, Alain, Li, You, Yu, Mickey, Tsai, Tsung-Che, Mitra, Souvick, Gauthier, JR., Robert J.
• Granted Patent: US 10,692,852 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 27/0262 including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/66393 Lateral or planar thyristors
• CPC Class Codes: H01L 29/7436 Lateral thyristors
• CPC Class Codes: H01L 29/87 Thyristor diodes, e.g. Shockley diodes, break-over diodes

Abstract

Silicon-controlled rectifiers and methods for forming a silicon-controlled rectifier. A first well of a first conductivity type is arranged in a substrate, and second and third wells of a second conductivity type are arranged in the substrate between the first well and the top surface of the substrate. A deep trench isolation region is laterally arranged between the first well of the second conductivity type and the second well of the second conductivity type. The second well is adjoined with the first well along a first interface, the third well is adjoined with the first well along a second interface, and the deep trench isolation region extends the top surface of the substrate past the first interface and the second interface and into the first well. A doped region of the first conductivity type is arranged in the substrate between the second well and the top surface of the substrate.

Claims

1. A device structure for a silicon-controlled rectifier, the device structure comprising:

a substrate having a top surface;

a first well of a first conductivity type arranged in the substrate;

a second well of a second conductivity type arranged in the substrate between the first well and the top surface of the substrate, the second well adjoined with the first well along a first interface;

a third well of the second conductivity type arranged in the substrate between the first well and the top surface of the substrate, the third well adjoined with the first well along a second interface;

a first deep trench isolation region laterally arranged in the substrate between the third well of the second conductivity type and the second well of the second conductivity type, the first deep trench isolation region extending from the top surface of the substrate past the first interface and the second interface and into the first well; and

a first doped region of the first conductivity type arranged in the substrate between the second well and the top surface of the substrate,

wherein the first well extends continuously beneath the first deep trench isolation region.

2. The device structure of claim 1 further comprising:

a doped region of the second conductivity type arranged in the substrate between the second well and the top surface of the substrate.

3. The device structure of claim 2 further comprising:

a shallow trench isolation region laterally arranged between the first doped region of the first conductivity type and the doped region of the second conductivity type, the shallow trench isolation region extending from the top surface of the substrate to the second well.

4. The device structure of claim 2 wherein the first doped region of the first conductivity type and the doped region of the second conductivity type are arranged in direct contact.

5. The device structure of claim 2 further comprising:

a second doped region of the first conductivity type arranged in the substrate between the third well and the top surface of the substrate.

6. The device structure of claim 1 further comprising:

a second doped region of the first conductivity type arranged in the substrate between the third well and the top surface of the substrate.

7. The device structure of claim 6 further comprising:

a doped region of the second conductivity type arranged in the substrate between the third well and the top surface of the substrate.

8. The device structure of claim 7 further comprising:

a shallow trench isolation region laterally arranged between the second doped region of the first conductivity type and the doped region of the second conductivity type, the shallow trench isolation region extending from the top surface of the substrate to the third well.

9. The device structure of claim 1 further comprising:

a second deep trench isolation region extending from the top surface of the substrate into the first well,

wherein the second well is laterally surrounded by the first deep trench isolation region and the second deep trench isolation region.

10. The device structure of claim 9 further comprising:

a third deep trench isolation region extending from the top surface of the substrate into the first well,

wherein the third well is laterally surrounded by the first deep trench isolation region and the third deep trench isolation region.

11. The device structure of claim 10 wherein the first well extends in part from the first deep trench isolation region to the second deep trench isolation region beneath the second well, and the first well extends in part from the second deep trench isolation region to the third deep trench isolation region beneath the third well.

12. The device structure of claim 1 wherein the first deep trench isolation region extends partially through the first well.

13. The device structure of claim 1 further comprising:

a fourth well of the second conductivity type arranged in the substrate between the first well and the top surface of the substrate;

a second deep trench isolation region laterally arranged between the second well of the second conductivity type and the fourth well of the second conductivity type, the second deep trench isolation region extending from the top surface of the substrate into the first well and to a greater depth in the substrate than the second well and the third well; and

a second doped region of the first conductivity type arranged in the substrate between the fourth well and the top surface of the substrate.

14. The device structure of claim 1 wherein the first conductivity type is n-type, and the second conductivity type is p-type.

15. A method for forming a device structure for a silicon-controlled rectifier, the method comprising:

forming a first well of a first conductivity type arranged in a substrate;

forming a second well of a second conductivity type and a third well of the second conductivity type each arranged in the substrate between the first well and a top surface of the substrate;

forming a first deep trench isolation region laterally arranged between the third well of the second conductivity type and the second well of the second conductivity type; and

forming a first doped region of the first conductivity type arranged in the substrate between the second well and the top surface of the substrate,

wherein the second well is adjoined with the first well along a first interface, the third well is adjoined with the first well along a second interface, the first deep trench isolation region extends from the top surface of the substrate past the first interface and the second interface and into the first well, and the first well extends continuously beneath the first deep trench isolation region.

16. The method of claim 15 further comprising:

forming a second deep trench isolation region extending from the top surface of the substrate into the first well,

wherein the second well is laterally surrounded by the first deep trench isolation region and the second deep trench isolation region.

17. The method of claim 16 further comprising:

forming a third deep trench isolation region extending from the top surface of the substrate into the first well,

wherein the third well is laterally surrounded by the first deep trench isolation region and the third deep trench isolation region.

18. The method of claim 17 wherein the first well extends in part from the first deep trench isolation region to the second deep trench isolation region beneath the second well, and the first well extends in part from the second deep trench isolation region to the third deep trench isolation region beneath the third well.

19. The method of claim 15 further comprising:

forming a doped region of the second conductivity type arranged in the substrate between the second well and the top surface of the substrate.

20. The method of claim 19 further comprising:

forming a shallow trench isolation region laterally arranged between the first doped region of the first conductivity type and the doped region of the second conductivity type,

wherein the shallow trench isolation region extends from the top surface of the substrate to the second well.