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ARCHITECTURE FOR MONOLITHIC 3D INTEGRATION OF SEMICONDUCTOR DEVICES

  • US 20200135718A1
  • Filed: 10/29/2019
  • Published: 04/30/2020
  • Est. Priority Date: 10/29/2018
  • Status: Active Grant
First Claim
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1. A three-dimensional (3D) integrated circuit (IC) comprising:

  • a substrate having a substrate surface;

    a power rail provided in the substrate;

    a first tier of semiconductor devices provided in the substrate and positioned over the power rail along a thickness direction of the substrate which is substantially perpendicular to said substrate surface;

    a wiring tier provided in the substrate and positioned over the first tier of semiconductor devices along the thickness direction;

    a second tier of semiconductor devices provided in the substrate and positioned over the wiring tier along the thickness direction, the second tier of semiconductor devices being stacked on the first tier of semiconductor devices in the thickness direction such that the wiring tier is interposed between the first and second tiers of semiconductor devices;

    a first vertical interconnect structure extending downward from the wiring tier to the first tier of semiconductor devices along the thickness direction to electrically connect the wiring tier to a device within the first tier of semiconductor devices; and

    a second vertical interconnect structure extending upward from the wiring tier to the second tier of semiconductor devices along the thickness direction to electrically connect the wiring tier to a device within the second tier of semiconductor devices.

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