FINFET STRUCTURE WITH DIELECTRIC BAR CONTAINING GATE TO REDUCE EFFECTIVE CAPACITANCE, AND METHOD OF FORMING SAME

• US 20200135723A1
• Filed: 10/25/2018
• Published: 04/30/2020
• Est. Priority Date: 10/25/2018
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Zang, Hui, Wang, Haiting, Tan, Chung Foong, Xu, Guowei, Xie, Ruilong, Beasor, Scott H., Jiang, Liu
• Granted Patent: US 10,797,049 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A FinFET structure having reduced effective capacitance and including a substrate having at least two fins thereon laterally spaced from one another, a metal gate over fin tops of the fins and between sidewalls of upper portions of the fins, source/drain regions in each fin on opposing sides of the metal gate, and a dielectric bar within the metal gate located between the sidewalls of the upper portions of the fins, the dielectric bar being laterally spaced away from the sidewalls of the upper portions of the fins within the metal gate.

Claims

1. A fin-type field effect transistor (FinFET) structure comprising:

a substrate having at least two fins thereon laterally spaced from one another;

a metal gate over fin tops of the at least two fins and between sidewalls of upper portions of the at least two fins;

source/drain regions in each fin on opposing sides of the metal gate; and

a dielectric bar within the metal gate located between the sidewalls of the upper portions of the at least two fins, the dielectric bar being laterally spaced away from the sidewalls of the upper portions of the at least two fins within the metal gate.

2. The FinFET structure of claim 1, further comprising a gate cut isolation extending from a portion of a top surface of the metal gate to at least a portion of a top surface of the dielectric bar.

3. The FinFET structure of claim 2, further comprising a shallow trench isolation (STI) layer on a top surface of the substrate and between sidewalls of lower portions of the at least two fins.

4. The FinFET structure of claim 3, wherein the gate cut isolation extending to the top surface of the dielectric bar has a depth that is less than a distance from the top surface of the metal gate to a top surface of the STI layer.

5. The FinFET structure of claim 4, wherein the gate cut isolation extending from the top surface of the metal gate to the top surface of the dielectric bar has a width that is less than a width of another gate cut isolation extending from the top surface of the metal gate to the top surface of the STI layer.

6. The FinFET structure of claim 1, wherein a vertical cross-sectional area of the metal gate is reduced by an amount equal to a vertical cross-sectional area of the dielectric bar within the metal gate.

7. The FinFET structure of claim 6, wherein the FinFET structure has an effective capacitance that is reduced by an amount proportional to the vertical cross-sectional area of the dielectric bar within the metal gate.

8. The FinFET structure of claim 1, wherein the dielectric bar is laterally spaced away from a given sidewall of the upper portion of a given fin by a distance of approximately 3.5 nanometers (nm) to approximately 10 nanometers (nm).

9-20. -20. (canceled)

21. An integrated circuit (IC) structure comprising:

a first fin-type field effect transistor (FinFET) on a substrate, the first FinFET including an upper surface and pair of sidewalls above the substrate;

a second FinFET on the substrate and laterally separated from the first FinFET, the second FinFET including an upper surface and pair of sidewalls above the substrate;

a shallow trench isolation (STI) on the substrate between the first FinFET and the second FinFET, wherein the STI includes a first vertical sidewall contacting the first FinFET and a second opposing vertical sidewall contacting the second FinFET; and

a dielectric bar on an upper surface of the STI, the dielectric bar being laterally spaced away from the first FinFET and the second FinFET.

22. The IC structure of claim 21, wherein each of the first FinFET and the second FinFET includes:

a semiconductor fin on the substrate;

a metal gate on the fin; and

a pair of source/drain regions within the fin on opposing sides of the metal gate.

23. The IC structure of claim 22, further comprising a gate cut isolation on an upper surface of the dielectric bar, wherein an upper surface of the gate cut isolation is substantially coplanar with an upper surface of the metal gate of the first FinFET or the second FinFET.

24. The IC structure of claim 22, wherein a vertical height of the gate cut isolation is less than a distance from a top surface of the metal gate to a top surface of the STI.

25. The IC structure of claim 21, wherein a vertical cross-sectional area of the dielectric bar is sized to reduce an effective capacitance of the first FinFET or the second FinFET.

26. The IC structure of claim 21, wherein the dielectric bar is laterally spaced away from each of the first FinFET and the second FinFET by a distance of approximately 3.5 nanometers (nm) to approximately 10 nanometers (nm).

27. An integrated circuit (IC) structure comprising:

a first fin-type field effect transistor (FinFET) on a substrate, the first FinFET including an upper surface and pair of sidewalls above the substrate;

a second FinFET on the substrate and laterally separated from the first FinFET, the second FinFET including an upper surface and pair of sidewalls above the substrate;

a shallow trench isolation (STI) on the substrate between the first FinFET and the second FinFET, wherein the STI includes a first vertical sidewall contacting the first FinFET and a second opposing vertical sidewall contacting the second FinFET;

a dielectric bar on an upper surface of the STI, the dielectric bar being laterally spaced away from the sidewalls of the first FinFET and the second FinFET; and

a gate cut isolation on an upper surface of the dielectric bar, wherein an upper surface of the gate cut isolation is substantially coplanar with an upper surface of the metal gate of the first FinFET and the second FinFET.

28. The IC structure of claim 27, wherein each of the first FinFET and the second FinFET includes:

a semiconductor fin on the substrate;

a metal gate on the fin contacting a sidewall of the gate cut isolation, wherein an upper surface of each metal gate defines an upper surface of the first FinFET or the second FinFET; and

a pair of source/drain regions within the fin on opposing sides of the metal gate.

29. The IC structure of claim 28, wherein a vertical cross-sectional area of the metal gate of the first FinFET or the second FinFET is reduced by an amount equal to a vertical cross-sectional area of the dielectric bar.

30. The IC structure of claim 29, wherein the first FinFET or the second FinFET has an effective capacitance that is reduced by an amount proportional to the vertical cross-sectional area of the dielectric bar.

31. The IC structure of claim 27, wherein the dielectric bar is laterally spaced away from each of the first FinFET and the second FinFET by a distance of approximately 3.5 nanometers (nm) to approximately 10 nanometers (nm).