Integrated Circuit Device Including a Power Supply Line and Method of Forming the Same

• US 20200135724A1
• Filed: 09/26/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Yi-Hsiung, Chang, Shang-Wen, Chiu, Yi-Hsun
• Granted Patent: US 11,063,041 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2027/11881 Power supply lines
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability

Abstract

A device includes a first semiconductor strip and a second semiconductor strip extending longitudinally in a first direction, where the first semiconductor strip and the second semiconductor strip are spaced apart from each other in a second direction. The device also includes a power supply line located between the first semiconductor strip and the second semiconductor strip. A top surface of the power supply line is recessed in comparison to a top surface of the first semiconductor strip. A source feature is disposed on a source region of the first semiconductor strip, and a source contact electrically couples the source feature to the power supply line. The source contact includes a lateral portion contacting a top surface of the source feature, and a vertical portion extending along a sidewall of the source feature towards the power supply line to physically contact the power supply line.

Claims

1. A device, comprising:

a first semiconductor strip extending longitudinally in a first direction;

a second semiconductor strip extending longitudinally in the first direction, the first semiconductor strip and the second semiconductor strip being spaced apart from each other in a second direction, the second direction being perpendicular to the first direction;

a power supply line located between the first semiconductor strip and the second semiconductor strip in the second direction, wherein a top surface of the power supply line is recessed in comparison to a top surface of the first semiconductor strip;

a source feature disposed on a source region of the first semiconductor strip; and

a source contact electrically coupling the source feature to the power supply line, the source contact including;

a lateral portion contacting a top surface of the source feature; and

a vertical portion extending along a sidewall of the source feature towards the power supply line to physically contact the power supply line.

2. The device of claim 1, wherein a dimension of a surface of the vertical portion of the source contact that physically contacts the power supply line is greater than 12 nanometers in the second direction.

3. The device of claim 1, wherein a dimension of the lateral portion of the source contact is in a range from about 8 nanometers to about 15 nanometers in the first direction.

4. The device of claim 1, wherein a dimension of the lateral portion of the source contact is in a range from about 15 nanometers to about 40 nanometers in the second direction.

5. The device of claim 1, further comprising:

a drain feature disposed on a drain region of the second semiconductor strip; and

a drain contact disposed on a top surface of the drain feature, wherein a top surface of the source contact is recessed in comparison with a top surface of the drain contact.

6. The device of claim 1, further comprising a first dielectric layer, the first dielectric layer lining sidewalls of the first semiconductor strip and the second semiconductor strip, the first dielectric layer further lining sidewalls of the power supply line.

7. The device of claim 6, further comprising a dielectric fin disposed on the power supply line.

8. The device of claim 7, wherein a material of the dielectric fin is different from a material of the first dielectric layer.

9. The device of claim 7, wherein the dielectric fin is adjacent to the vertical portion of the source contact in the second direction.

10. A method, comprising:

forming a first device fin structure and a second device fin structure on a substrate, the first device fin structure being laterally adjacent to the second device fin structure;

depositing a first dielectric layer on the first device fin structure and the second device fin structure, the first dielectric layer defining a trench disposed between the first device fin structure and the second device fin structure;

forming a power supply line in the trench;

forming a source feature and a drain feature on the first device fin structure and the second device fin structure, respectively;

forming a source contact to couple the source feature to the power supply line, the source contact including;

a first portion contacting a top surface of the source feature; and

a second portion extending from a peripheral region of the first portion towards the power supply line to physically contact the power supply line.

11. The method of claim 10, wherein a top surface of the power supply line is recessed in comparison to the top surface of the source feature.

12. The method of claim 10, wherein forming the source contact includes:

forming a fill fin over the power supply line, the fill fin being disposed between the source feature and the drain feature;

depositing a second dielectric layer over the first dielectric layer, the source feature, the drain feature, and the fill fin;

removing portions of the fill fin and the second dielectric layer to form a slot opening, the slot opening exposing the top surface of the source feature and a portion of a top surface of the power supply line; and

depositing one or more conductive materials in the slot opening.

13. The method of claim 12, wherein removing portions of the fill fin and the second dielectric layer to form the slot opening comprises an anisotropic etch process.

14. The method of claim 13, wherein the anisotropic etch process uses a fluorine-containing etchant, a chlorine-containing etchant, or a combination thereof.

15. The method of claim 12, wherein a material of the fill fin is different from a material of the first dielectric layer.

16. The method of claim 10, wherein a sidewall of the second portion of the source contact is aligned with a sidewall of the power supply line.

17. A device, comprising:

a well region;

a first transistor device disposed within a boundary of the well region, the first transistor device including a first fin structure extending lengthwise in a first direction;

a second transistor device disposed within the boundary of the well region, the second transistor device including a second fin structure extending lengthwise in the first direction, the first transistor device being spaced apart from the second transistor device in a second direction, the second direction being perpendicular to the first direction;

an insulating region disposed between the first fin structure and the second fin structure in the second direction;

a power supply line disposed within the insulating region, wherein the power supply line is recessed, in a third direction, in comparison to a source feature of the first transistor device, the third direction being perpendicular to the first direction and the second direction; and

a source contact coupling the source feature of the first transistor device to the power supply line, the source contact including;

a first portion disposed on a surface of the source feature directed away from the well region; and

a second portion extending continuously from the first portion in the third direction to physically contact the power supply line.

18. The device of claim 17, wherein a dimension of a surface of the second portion of the source contact that physically contacts the power supply line is greater than 12 nanometers in the second direction.

19. The device of claim 17, wherein a sidewall of the second portion of the source contact is substantially aligned with a sidewall of the power supply line.

20. The device of claim 17, further comprising a silicide layer disposed between the first portion of the source contact and the surface of the source feature directed away from the well region.