Semiconductor Device Having Fins

• US 20200135726A1
• Filed: 12/20/2019
• Published: 04/30/2020
• Est. Priority Date: 04/28/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Fan, Chia-Sheng, Young, Bao-Ru, Hsieh, Tung-Heng
• Granted Patent: US 10,991,691 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/0223 formation by oxidation, e.g. oxidation of the substrate
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not

Abstract

A semiconductor device and method includes: forming a first fin and a second fin on a substrate; forming a dummy gate material over the first fin and the second fin; forming a recess in the dummy gate material between the first fin and the second fin; forming a sacrificial oxide on sidewalls of the dummy gate material in the recess; filling an insulation material between the sacrificial oxide on the sidewalls of the dummy gate material in the recess; removing the dummy gate material and the sacrificial oxide; and forming a first replacement gate over the first fin and a second replacement gate over the second fin.

Claims

1. A device comprising:

a first fin extending from a substrate;

a first gate stack on the first fin;

a second fin extending from the substrate;

a second gate stack on the second fin; and

a first isolation region disposed between the first gate stack and the second gate stack, the first isolation region comprising;

a first edge portion;

a second edge portion; and

a middle portion disposed between the first edge portion and the second edge portion along a first direction, the middle portion being narrower than each of the first edge portion and the second edge portion along a second direction, the first direction being parallel to longitudinal axes of the first fin and the second fin, the second direction being perpendicular to the first direction.

2. The device of claim 1 further comprising:

a first gate spacer extending along first sidewalls of the first gate stack, the second gate stack, and the first edge portion of the first isolation region; and

a second gate spacer extending along second sidewalls of the first gate stack, the second gate stack, and the second edge portion of the first isolation region.

3. The device of claim 1, wherein the first gate stack comprises a first gate dielectric on the first fin, and a first gate electrode on the first gate dielectric, wherein the second gate stack comprises a second gate dielectric on the second fin, and a second gate electrode on the second gate dielectric, and wherein the first gate dielectric and the second gate dielectric extend along sidewalls of the first isolation region.

4. The device of claim 3, wherein each of the sidewalls of the first isolation region form an obtuse angle with a plane parallel to a major surface of the substrate.

5. The device of claim 4, wherein the obtuse angle is in a range of 92 degrees to 97 degrees.

6. The device of claim 1, wherein the first isolation region comprises silicon nitride.

7. The device of claim 1 further comprising:

a second isolation region surrounding the first fin and the second fin, the second isolation region disposed between the first isolation region and the substrate.

8. The device of claim 7, wherein the first isolation region and the second isolation region comprise the same dielectric material.

9. The device of claim 7, wherein the first isolation region and the second isolation region comprise different dielectric materials.

10. A device comprising:

a first fin extending from a substrate;

a second fin extending from the substrate;

a first gate spacer over the first fin and the second fin;

a second gate spacer over the first fin and the second fin; and

a first isolation region disposed between the first gate spacer and the second gate spacer, the first isolation region comprising;

a first edge portion contacting the first gate spacer;

a second edge portion contacting the second gate spacer; and

a middle portion disposed between the first edge portion and the second edge portion along a first direction, the middle portion being narrower than each of the first edge portion and the second edge portion along a second direction, the first direction extending from the first gate spacer to the second gate spacer, the second direction being perpendicular to the first direction.

11. The device of claim 10 further comprising:

a first gate stack on the first fin; and

a second gate stack on the second fin, the second gate stack separated from the first gate stack by the first isolation region.

12. The device of claim 10, wherein the first isolation region comprises silicon nitride.

13. The device of claim 10 further comprising:

a second isolation region surrounding the first fin and the second fin, the second isolation region disposed between the first isolation region and the substrate.

14. The device of claim 13, wherein the first isolation region and the second isolation region comprise the same dielectric material.

15. The device of claim 13, wherein the first isolation region and the second isolation region comprise different dielectric materials.

16. A method comprising:

forming a first fin and a second fin extending from a substrate;

forming a dummy gate dielectric on the first fin and the second fin;

forming a dummy gate electrode on the dummy gate dielectric;

patterning an opening in the dummy gate electrode and the dummy gate dielectric, the opening disposed between the first fin and the second fin;

oxidizing sidewalls of the dummy gate electrode to form sacrificial oxides in the opening;

forming a first isolation region between the sacrificial oxides in the opening;

removing the dummy gate electrode with a first etch; and

after removing the dummy gate electrode, removing the dummy gate dielectric and the sacrificial oxides with a second etch, the second etch being selective to materials of the dummy gate dielectric and the sacrificial oxides.

17. The method of claim 16 further comprising:

after removing the dummy gate dielectric and the sacrificial oxides, depositing a gate dielectric layer on the first fin, the second fin, and the first isolation region;

depositing a gate electrode layer on the gate dielectric layer; and

planarizing the gate electrode layer and the gate dielectric layer, top surfaces of the gate electrode layer, the gate dielectric layer, and the first isolation region being planar.

18. The method of claim 16 further comprising:

forming gate spacers along the dummy gate electrode; and

forming source/drain regions, each one of the source/drain regions being separated from the dummy gate electrode by one of the gate spacers.

19. The method of claim 18, wherein after patterning the opening, the opening has a first width proximate the gate spacers and a second width distal the gate spacers, the first width being greater than the second width.

20. The method of claim 16 further comprising:

depositing a second isolation region around the first fin and the second fin, the opening exposing the second isolation region after patterning the opening.