SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME

• US 20200135727A1
• Filed: 12/20/2019
• Published: 04/30/2020
• Est. Priority Date: 01/29/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: CHEN, Fang, LIAW, Jhon Jhy, LIANG, Min-Chang
• Granted Patent: US 11,127,742 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device includes a fin field effect transistor. The semiconductor device includes a first gate electrode, a first source/drain (S/D) region disposed adjacent to the first gate electrode, a first S/D contact disposed on the first S/D region, a first spacer layer disposed between the first gate electrode and the first S/D region, a first contact layer in contact with the first gate electrode and the first S/D contact, and a first wiring layer integrally formed with the first contact layer. There is no interface between the first contact layer and the first wiring layer in a cross sectional view, and the first contact layer has a smaller area than the first wiring layer in plan view.

Claims

1. A semiconductor device, comprising:

a fin structure;

a first gate electrode disposed over a first part of the fin structure;

a second gate electrode disposed over a second part of the fin structure;

a first source/drain (S/D) region disposed adjacent to the first gate electrode;

a second S/D region disposed adjacent to the second gate electrode;

a first contact layer in electrically contact with the first gate electrode and the first S/D region;

a second contact layer in electrically contact with the second gate electrode; and

a third contact layer in electrically contact with the second S/D region, wherein;

the third contact layer is disposed above the second part of the fin structure, and

the second contact layer is not disposed above the fin structure.

2. The semiconductor device of claim 1, wherein the second contact layer is disposed above an isolation insulating layer from which the fin structure protrudes.

3. The semiconductor device of claim 1, wherein the first contact layer is disposed above the first part of the fin structure.

4. The semiconductor device of claim 1, wherein the first contact layer is disposed above an isolation insulating layer from which the fin structure protrudes.

5. The semiconductor device of claim 1, wherein the second contact layer is a contact layer closest to the third contact layer in a plan view.

6. The semiconductor device of claim 1, further comprising a first S/D contact disposed between the first contact layer and the first S/D region,

wherein the first S/D contact is not in direct contact with the first gate electrode.

7. The semiconductor device of claim 6, wherein the first contact layer is in direct contact with the first gate electrode and an uppermost portion and a side face of the first S/D contact.

8. The semiconductor device of claim 6, further comprising:

first gate sidewall spacers disposed on opposite side faces of the first gate electrode; and

a first spacer layer made of an insulating material and disposed between one of the first gate sidewall spacers and the first S/D contact,

wherein a bottom surface of the first contact layer is in contact with an upper surface of the first spacer layer and an upper surface of the one of the first gate sidewall spacers.

9. The semiconductor device of claim 1, further comprising a first gate cap insulating layer formed over the first gate electrode,

wherein a side surface of the first contact layer is in contact with the first gate cap insulating layer.

10. The semiconductor device of claim 9, further comprising:

a first interlayer dielectric layer disposed over at least the first cap insulating layer; and

a first wiring layer integrally formed with the first contact layer, wherein;

the first contact layer has a smaller area than the first wiring layer in plan view,

the first wiring layer is embedded in an upper portion of the first interlayer dielectric layer, and

the first contact layer penetrates a bottom portion of the first interlayer dielectric layer and the first gate cap insulating layer.

11. The semiconductor device of claim 10, further comprising:

a second gate cap insulating layer formed over the second gate electrode; and

a second wiring layer integrally formed with the second contact layer, wherein;

the second wiring layer is embedded in the upper portion of the first interlayer dielectric layer, and

the second contact layer penetrates the bottom portion of the first interlayer dielectric layer and the second gate cap insulating layer.

12. The semiconductor device of claim 11, further comprising:

a third wiring layer integrally formed with the third contact layer, wherein;

there is no interface between the third contact layer and the third wiring layer in a cross sectional view,

the third wiring layer is embedded in the upper portion of the first interlayer dielectric layer, and

the third contact layer penetrates the bottom portion of the first interlayer dielectric layer.

13. A semiconductor device, comprising:

a fin structure;

a first gate electrode disposed over a first part of the fin structure;

a second gate electrode disposed over a second part of the fin structure;

a first gate contact layer disposed on the first gate electrode;

a second gate contact layer disposed on the second gate electrode;

a first source/drain (S/D) region;

a second S/D region;

a first S/D contact in electrically contact with the first S/D region;

a second S/D contact in electrically contact with the second S/D region;

a first contact layer in electrically contact with the first gate contact layer and the first S/D contact;

a second contact layer in electrically contact with the second gate contact layer;

a third contact layer in electrically contact with the second S/D contact;

a first insulating layer disposed over the first gate contact, the second gate contact, the first S/D contact and the second S/D contact; and

a second insulating layer disposed over the first insulating layer and made of a different material than the first insulating layer,

wherein side faces of the first, second and third contact layer are in direct contact with the first and second insulating layers.

14. The semiconductor device of claim 13, wherein:

the third contact layer is disposed above the second part of the fin structure, and

the second contact layer is disposed above an isolation insulating layer from which the fin structure protrudes.

15. The semiconductor device of claim 14, wherein:

the first contact layer is in direct contact with an uppermost portion of the first gate contact layer and an uppermost portion of the first S/D contact, and

the first S/D contact is not in direct contact with the first gate electrode.

16. The semiconductor device of claim 14, wherein the first contact layer is disposed above the first part of the fin structure.

17. The semiconductor device of claim 14, wherein the first contact layer is disposed above the isolation insulating layer.

18. The semiconductor device of claim 14, wherein the second contact layer is a contact layer closest to the third contact layer in a plan view.

19. A semiconductor device, comprising:

a fin structure;

a first gate electrode disposed over the fin structure;

a second gate electrode disposed over the fin structure;

a first source/drain (S/D) region disposed on the fin structure;

a second source/drain (S/D) region disposed on the fin structure;

a first contact layer in electrically contact with the first gate electrode and the first S/D region;

a second contact layer in electrically contact with the second gate electrode; and

a third contact layer in electrically contact with the second S/D region, wherein;

the third contact layer is disposed above the fin structure,

the second contact layer is disposed above an isolation insulating layer from which the fin structure protrudes, and

the second contact layer is a closest contact layer to the third contact layer in plan view.

20. The semiconductor device of claim 19, wherein a bottom of the first contact layer is located below a bottom of the second contact layer and a bottom of the third contact layer.