SEMICONDUCTOR DEVICE

• US 20200135728A1
• Filed: 12/23/2019
• Published: 04/30/2020
• Est. Priority Date: 03/18/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: LIAW, Jhon-Jhy
• Granted Patent: US 11,043,490 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7855 with at least two independent gates
• CPC Class Codes: H01L 29/7856 with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides H01L29/7855 takes precedence
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: H10B 12/36 the transistor being a FinFET

Abstract

A semiconductor device includes a dielectric dummy gate, a plurality of first semiconductor fins, and a plurality of second semiconductor fins. The dielectric dummy gate extends along a first direction. The first semiconductor fins extend along a second direction within a first core circuit region on a first side of the dielectric dummy gate, and the second direction is substantially perpendicular to the first direction. The second semiconductor fins extend along the second direction within a second core circuit region on a second side of the dielectric dummy gate opposite the first side of the dielectric dummy gate. A number of the second semiconductor fins within the second core circuit region is less than a number of the first semiconductor fins within the first core circuit region, and each of the second semiconductor fins has a width less than a width of each of the first semiconductor fins.

Claims

1. A semiconductor device, comprising:

a dielectric dummy gate extending along a first direction;

a plurality of first semiconductor fins extending along a second direction within a first core circuit region on a first side of the dielectric dummy gate, the second direction being substantially perpendicular to the first direction; and

a plurality of second semiconductor fins extending along the second direction within a second core circuit region on a second side of the dielectric dummy gate opposite the first side of the dielectric dummy gate, wherein a number of the second semiconductor fins within the second core circuit region is less than a number of the first semiconductor fins within the first core circuit region, and each of the second semiconductor fins has a width less than a width of each of the first semiconductor fins.

2. The semiconductor device of claim 1, wherein the first semiconductor fins are arranged along the first direction by a first pitch, and the second semiconductor fins are arranged along the first direction by a second pitch greater than the first pitch.

3. The semiconductor device of claim 1, further comprising:

a spacer on the first side of the dielectric dummy gate, and overlapping longitudinal ends of the first semiconductor fins.

4. The semiconductor device of claim 1, further comprising:

a spacer on the second side of the dielectric dummy gate, and overlapping longitudinal ends of the second semiconductor fins.

5. The semiconductor device of claim 1, further comprising:

a spacer enclosing the dielectric dummy gate when viewed from above.

6. The semiconductor device of claim 1, further comprising:

a first gate dielectric layer extending across the first semiconductor fins; and

a second gate dielectric layer extending across the second semiconductor fins and having a thickness comparable to a thickness of the first gate dielectric layer.

7. The semiconductor device of claim 6, further comprising:

a third gate dielectric layer of an I/O device having a thickness greater than the thickness of the first gate dielectric layer and the thickness of the second gate dielectric layer.

8. The semiconductor device of claim 1, further comprising:

a first contact and a second contact extending within the first core circuit region and across both the first semiconductor fins; and

a third contact and a fourth contact extending within the second core circuit region and across one of the second semiconductor fins.

9. The semiconductor device of claim 8, wherein a length difference between the third and fourth contacts is greater than a length difference between the first and second contacts, the length differences are measured in the first direction.

10. The semiconductor device of claim 8, further comprising:

a metal gate extending within the first core circuit region and between the first and second contacts, wherein the metal gate has a length comparable to a length of the dielectric dummy gate, and the lengths are measured in the first direction.

11. The semiconductor device of claim 8, further comprising:

a metal gate extending within the second core circuit region and between the third and fourth contacts, wherein the metal gate has a length comparable to a length of the dielectric dummy gate, and the lengths are measured in the first direction.

12. A semiconductor device, comprising:

a first core circuit comprising a plurality first semiconductor fins and a first source/drain contact extending a first length across the first semiconductor fins; and

a second core circuit electrically isolated from the first core circuit by a dielectric dummy gate, the second core circuit comprising a second semiconductor fin and a second source/drain contact extending a second length across the second semiconductor fin, wherein the second length of the second source/drain contact is less than the first length of the first source/drain contact, and each of the first semiconductor fins has a width greater than a width of the second semiconductor fin.

13. The semiconductor device of claim 12, wherein a ratio of the first length of the first source/drain contact to the second length of the second source/drain contact is in a range from about 1.1 to about 3.

14. The semiconductor device of claim 12, wherein a ratio of the width of each of the first semiconductor fins to the width of the second semiconductor fin is equal to or greater than about 1.05.

15. The semiconductor device of claim 12, further comprising:

a first gate dielectric layer extending across the first semiconductor fins; and

a second gate dielectric layer extending across the second semiconductor fin and having a thickness comparable to a thickness of the first gate dielectric layer.

16. A semiconductor device, comprising:

an I/O circuit comprising a first semiconductor fin;

a first core circuit comprising a second semiconductor fin; and

a second core circuit comprising a third semiconductor fin, wherein a width of the third semiconductor fin is greater than a width of the first semiconductor fin of the I/O circuit and less than a width of the second semiconductor fin of the first core circuit.

17. The semiconductor device of claim 16, wherein a thickness of a gate dielectric layer in the I/O circuit is greater than a thickness of a gate dielectric layer in the first core circuit.

18. The semiconductor device of claim 16, wherein a thickness of a gate dielectric layer in the I/O circuit is greater than a thickness of a gate dielectric layer in the second core circuit.

19. The semiconductor device of claim 16, wherein the I/O circuit comprises a plurality of the first semiconductor fins arranged at a first pitch, the first core circuit comprises a plurality of the second semiconductor fins arranged at a second pitch comparable to the first pitch.

20. The semiconductor device of claim 19, wherein the second core circuit comprises a plurality of the third semiconductor fins arranged at a third pitch greater than the second pitch.