DOUBLE RULE INTEGRATED CIRCUIT LAYOUTS FOR A DUAL TRANSMISSION GATE

• US 20200135732A1
• Filed: 12/26/2019
• Published: 04/30/2020
• Est. Priority Date: 06/28/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: PENG, Shih-Wei, ZHUANG, Hui-Zhong, TZENG, Jiann-Tyng, TIEN, Li-Chun, SUE, Pin-Dai, LIN, Wei-Cheng
• Granted Patent: US 10,868,008 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/122 in field-effect transistor switches
• CPC Class Codes: H03K 17/6872 using complementary field-effect transistors
• CPC Class Codes: H03K 2217/0054 Gating switches, e.g. pass gates

Abstract

Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor. These exemplary integrated circuit layouts disclose various configurations and arrangements of various geometric shapes that are situated within an oxide diffusion (OD) layer, a polysilicon layer, a metal diffusion (MD) layer, the first metal layer, and/or a second metal layer of a semiconductor stack. In the exemplary embodiments to follow, the various geometric shapes within the first metal layer are situated within the multiple rows of the electronic device design real estate and the various geometric shapes within the OD layer, the polysilicon layer, the MD layer, and/or the second metal layer are situated within multiple columns of the electronic device design real estate.

Claims

1. A dual transmission gate, comprising:

a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, situated within a first column from among a plurality of columns of an electronic device design real estate, arranged to form a first transmission gate, the first transmission gate being configured to route a first signal between a first terminal and a second terminal in response to a first clocking signal being at a first logical level and a second clocking signal being at a second logical level;

a second pair of CMOS transistors, situated within a second column from among the plurality of columns, arranged to form a second transmission gate, the second transmission gate being configured to route a second signal between the second terminal and a third terminal in response to the first clocking signal being at the second logical level and the second clocking signal being at the first logical level;

a first region and a second region corresponding to the first clocking signal situated within a first interconnection layer of a semiconductor stack along a first row and a second row, respectively, from among a plurality of rows of the electronic device design real estate;

a third region, situated within a second interconnection layer of the semiconductor stack along a third column from among the plurality of columns, connected to the first region and the second region;

a fourth region and a fifth region corresponding to the second clocking signal situated within the first interconnection layer of the semiconductor stack along a third row and a fourth row, respectively, from among the plurality of rows; and

a sixth region, situated within the second interconnection layer of the semiconductor stack along a fourth column from among the plurality of columns, connected to the fourth region and the fifth region.

2. The dual transmission gate of claim 1, wherein the first interconnection layer comprises:

a first metal layer of the semiconductor stack, and

wherein the second interconnection layer comprises;

a polysilicon layer of the semiconductor stack;

an oxide diffusion (OD) layer of the semiconductor stack;

or

a second metal layer of the semiconductor stack.

3. The dual transmission gate of claim 1, wherein a length of the third region is equal to a length of the sixth region.

4. The dual transmission gate of claim 1, wherein the first pair of CMOS transistors comprises:

a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor situated within the first row; and

a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor situated within the third row, and

wherein the second pair of CMOS transistors comprises

a second PMOS transistor situated within the second row; and

a second NMOS transistor situated within the fourth row.

5. The dual transmission gate of claim 4, further comprising:

a seventh region corresponding to the first terminal situated along a fifth column from among the plurality of columns, the seventh region being connected to a first source/drain region of the first PMOS transistor and a first source/drain region of the first NMOS transistor;

an eighth region corresponding to the third terminal situated along a sixth column from among the plurality of columns, the eighth region being connected to a first source/drain region of the second PMOS transistor and a first source/drain region of the second NMOS transistor; and

a ninth region corresponding to the second terminal situated along a seventh column from among the plurality of columns, the ninth region connected to a second source/drain region of the first PMOS transistor, a second source/drain region of the first NMOS transistor, a second source/drain region of the second PMOS transistor, and a second source/drain region of the second NMOS transistor.

6. The dual transmission gate of claim 4, wherein the first region is connected to a first region of polysilicon material situated within a polysilicon layer of the semiconductor stack along the first column, the first region of polysilicon material being connected to a gate region of the first PMOS transistor,

wherein the second region is connected to a second region of polysilicon material situated within the polysilicon layer along the second column, the second region of polysilicon material being connected to a gate region of the second PMOS transistor,

wherein the fourth region is connected to a third region of polysilicon material situated within the polysilicon layer along the first column, the third region of polysilicon material being connected to a gate region of the first PMOS transistor, and

wherein the fifth region is connected to a fourth region of polysilicon material situated within the polysilicon layer along the second column, the fourth region of polysilicon material being connected to a gate region of the second NMOS transistor.

7. A dual transmission gate, comprising:

a first pair of transistors situated within a first column from among a plurality of columns of an electronic device design real estate, a first transistor from among the first pair of transistors being situated along a first row from among a plurality of rows of the electronic device design real estate and a second transistor from among the first pair of transistors being situated along a second row from among the plurality of rows;

a second pair of transistors situated within a second column from among the plurality of columns, a third transistor from among the second pair of transistors being situated along a third row from among the plurality of rows and a fourth transistor from among the second pair of transistors being situated along a fourth row from among the plurality of rows;

a first region and a second region situated within a first interconnection layer of the semiconductor stack along the first row and the third row;

a third region, situated within a second interconnection layer of the semiconductor stack along a third column from among a plurality of columns, connecting the first region and the second region;

a fourth region and a fifth region situated within the first interconnection layer of the semiconductor stack along the second row and the fourth row, respectively; and

a sixth region, situated within the second interconnection layer of the semiconductor stack along a fourth column from among the plurality of columns connecting the fourth region and the fifth region.

8. The dual transmission gate of claim 7, wherein the first interconnection layer comprises:

a first metal layer of the semiconductor stack, and

wherein the second interconnection layer comprises;

a polysilicon layer of the semiconductor stack;

an oxide diffusion (OD) layer of the semiconductor stack;

or

a second metal layer of the semiconductor stack.

9. The dual transmission gate of claim 7, wherein a length of the third region is equal to a length of the sixth region.

10. The dual transmission gate of claim 7, wherein the first transistor comprises:

a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor,

wherein the second transistor comprises;

a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and

wherein the third transistor comprises;

a second PMOS transistor situated within the second row, and

wherein the fourth transistor comprises;

a second NMOS transistor situated within the fourth row.

11. The dual transmission gate of claim 10, further comprising:

a seventh region situated along a fifth column from among the plurality of columns, the seventh region being connected to a first source/drain region of the first PMOS transistor and a first source/drain region of the first NMOS transistor;

an eighth region situated along a sixth column from among the plurality of columns, the eighth region being connected to a first source/drain region of the second PMOS transistor and a first source/drain region of the second NMOS transistor; and

a ninth region along a seventh column from among the plurality of columns, the ninth region being connected to a second source/drain region of the first PMOS transistor, a second source/drain region of the first NMOS transistor, a second source/drain region of the second PMOS transistor, and a second source/drain region of the second NMOS transistor.

12. The dual transmission gate of claim 7, wherein the first region is connected to a first region of polysilicon material situated within a polysilicon layer of the semiconductor stack along the first column, the first region of polysilicon material being connected to a gate region of the first transistor,

wherein the second region is connected to a second region of polysilicon material situated within the polysilicon layer along the second column, the second region of polysilicon material being connected to a gate region of the third transistor,

wherein the fourth region is connected to a third region of polysilicon material situated within the polysilicon layer along the first column, the third region of polysilicon material being connected to a gate region of the second transistor, and

wherein the fifth region is connected to a fourth region of polysilicon material situated within the polysilicon layer along the second column, the fourth region of polysilicon material being connected to a gate region of the fourth transistor.

13. The dual transmission gate of claim 7, wherein the first pair of transistors is arranged to form a first transmission gate, and

wherein the second pair of transistors is arranged to form a second transmission gate.

14. A dual transmission gate, comprising:

a first region and a second region situated within a first interconnection layer of a semiconductor stack along a first row and a second row, respectively, from among a plurality of rows of the electronic device design real estate;

a first pair of transistors, situated within a first column from among a plurality of columns of the electronic device design real estate, a first transistor from among the first pair of transistors being connected to the first region and a second transistor from among the first pair of transistors being connected to the second region;

a third region and a fourth region situated within the first interconnection layer along a third row and a fourth row, respectively, from among the plurality of rows;

a second pair of transistors, situated within a second column from among the plurality of columns, a third transistor from among the second pair of transistors being connected to the third region and a fourth transistor from among the second pair of transistors being connected to the fourth region; and

a fifth region and a sixth region, situated within a second interconnection layer of the semiconductor stack along a third column and a fourth column, respectively, from among the plurality of columns, the fifth region connecting the first region and the third region and the sixth region connecting the second region and the fourth region.

15. The dual transmission gate of claim 14, wherein the first interconnection layer comprises:

a first metal layer of the semiconductor stack, and

wherein the second interconnection layer comprises;

a polysilicon layer of the semiconductor stack;

an oxide diffusion (OD) layer of the semiconductor stack;

or

a second metal layer of the semiconductor stack.

16. The dual transmission gate of claim 14, wherein a length of the fifth region is equal to a length of the sixth region.

17. The dual transmission gate of claim 14, wherein the first transistor comprises:

a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor,

wherein the second transistor comprises;

a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and

wherein the third transistor comprises;

a second PMOS transistor situated within the second row, and

wherein the fourth transistor comprises;

a second NMOS transistor situated within the fourth row.

18. The dual transmission gate of claim 17, further comprising:

a seventh region situated along a fifth column from among the plurality of columns, the seventh region being connected to a first source/drain region of the first PMOS transistor and a first source/drain region of the first NMOS transistor;

an eighth region situated along a sixth column from among the plurality of columns, the eighth region being connected to a first source/drain region of the second PMOS transistor and a first source/drain region of the second NMOS transistor; and

a ninth region along a seventh column from among the plurality of columns, the ninth region being connected to a second source/drain region of the first PMOS transistor, a second source/drain region of the first NMOS transistor, a second source/drain region of the second PMOS transistor, and a second source/drain region of the second NMOS transistor.

19. The dual transmission gate of claim 14, wherein the first region is connected to a first region of polysilicon material situated within a polysilicon layer of the semiconductor stack along the first column, the first region of polysilicon material being connected to a gate region of the first transistor,

wherein the second region is connected to a second region of polysilicon material situated within the polysilicon layer along the second column, the second region of polysilicon material being connected to a gate region of the third transistor,

wherein the fourth region is connected to a third region of polysilicon material situated within the polysilicon layer along the first column, the third region of polysilicon material being connected to a gate region of the second transistor, and

wherein the fifth region is connected to a fourth region of polysilicon material situated within the polysilicon layer along the second column, the fourth region of polysilicon material being connected to a gate region of the fourth transistor.

20. The dual transmission gate of claim 14, wherein the first pair of transistors is arranged to form a first transmission gate, and

wherein the second pair of transistors is arranged to form a second transmission gate.