APPARATUS AND CIRCUITS WITH DUAL THRESHOLD VOLTAGE TRANSISTORS AND METHODS OF FABRICATING THE SAME

• US 20200135733A1
• Filed: 09/19/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: CHERN, Chan-Hong
• Granted Patent: US 11,682,676 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/085 including field-effect components only
• CPC Class Codes: H01L 27/095 the components being Schottky barrier gate field-effect transistors
• CPC Class Codes: H01L 27/098 the components being PN junction gate field-effect transistors
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/475 on AIII-BV compounds
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
• CPC Class Codes: H03K 17/161 in field-effect transistor switches
• CPC Class Codes: H03K 17/302 in field-effect transistor switches

Abstract

Apparatus and circuits with dual threshold voltage transistors and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a first layer comprising a first III-V semiconductor material formed over the substrate; a first transistor formed over the first layer, and a second transistor formed over the first layer. The first transistor comprises a first gate structure comprising a first material, a first source region and a first drain region. The second transistor comprises a second gate structure comprising a second material, a second source region and a second drain region. The first material is different from the second material.

Claims

1. A semiconductor structure, comprising:

a substrate;

a first layer comprising a first III-V semiconductor material formed over the substrate;

a first transistor formed over the first layer, wherein the first transistor comprises a first gate structure comprising a first material, a first source region and a first drain region; and

a second transistor formed over the first layer, wherein the second transistor comprises a second gate structure comprising a second material, a second source region and a second drain region, wherein the first material is different from the second material.

2. The semiconductor structure of claim 1, wherein:

the first transistor and the second transistor are high electron mobility transistors to be used in a same multi-stage driver circuit.

3. The semiconductor structure of claim 1, wherein:

the first transistor has a first threshold voltage; and

the second transistor has a second threshold voltage that is lower than the first threshold voltage.

4. The semiconductor structure of claim 3, wherein:

the first material has a lower work-function than the second material.

5. The semiconductor structure of claim 4, wherein:

the first material comprises at least one of;

tungsten (W) and titanium/tungsten/titanium-nitride (Ti/W/TiN) metal stack; and

the second material comprises at least one of;

nickel (Ni) and titanium/nickel/titanium-nitride (Ti/Ni/TiN) metal stack.

6. The semiconductor structure of claim 1, further comprising a second layer comprising a second III-V semiconductor material disposed on the first layer, wherein:

the second III-V semiconductor material is different from the first III-V semiconductor material;

the first gate structure is formed over the second III-V semiconductor material and between the first source region and the first drain region; and

the second gate structure is formed over the second III-V semiconductor material and between the second source region and the second drain region.

7. The semiconductor structure of claim 6, wherein:

the first semiconductor material comprises gallium nitride (GaN); and

the second III-V semiconductor material comprises aluminum gallium nitride (AlGaN).

8. The semiconductor structure of claim 6, further comprising a polarization modulation layer disposed on the second layer, wherein:

the polarization modulation layer comprises p-type doped GaN; and

the first gate structure and the second gate structure are disposed on the polarization modulation layer.

9. A circuit, comprising:

a first transistor including a first gate, a first source and a first drain; and

a second transistor including a second gate, a second source and a second drain, wherein;

the first transistor and the second transistor are formed on a same semiconductor wafer, and

the second gate is made of a material that is different from that of the first gate.

10. The circuit of claim 9, wherein:

the first transistor has a first threshold voltage; and

the second transistor has a second threshold voltage that is different from the first threshold voltage.

11. The circuit of claim 9, wherein:

at least one of the first source and the first drain is electrically connected to a ground voltage; and

at least one of the second source and the second drain is electrically connected to a positive power supply voltage.

12. The circuit of claim 11, wherein:

the first threshold voltage is higher than the second threshold voltage.

13. The circuit of claim 12, wherein:

the first gate is made of a first material;

the second gate is made of a second material; and

the first material has a lower work-function than the second material.

14. The circuit of claim 12, wherein:

at least one of the first source and the first drain is electrically connected to an output pin of the circuit.

15. The circuit of claim 12, wherein the first transistor is at least one of:

a high voltage enhancement-mode high electron mobility transistor (HV E-HEMT);

a low voltage enhancement-mode high electron mobility transistor (LV E-HEMT); and

a low voltage depletion-mode high electron mobility transistor (LV D-HEMT).

16. The circuit of claim 12, wherein the second transistor is a low voltage enhancement-mode high electron mobility transistor (LV E-HEMT).

17. The circuit of claim 9, wherein the first gate is physically coupled to the second source.

18. A method for forming a semiconductor structure, comprising:

forming a first layer comprising a first III-V semiconductor material over a semiconductor substrate;

forming a first transistor over the first layer, wherein the first transistor comprises a first gate structure comprising a first material, a first source region and a first drain region; and

forming a second transistor over the first layer, wherein the second transistor comprises a second gate structure comprising a second material, a second source region and a second drain region, wherein the first material is different from the second material.

19. The method of claim 18, wherein:

the first transistor and the second transistor are high electron mobility transistors to be used in a same multi-stage driver circuit;

the first transistor has a first threshold voltage;

the second transistor has a second threshold voltage that is lower than the first threshold voltage; and

the first material has a lower work-function than the second material.

20. The method of claim 18, further comprising disposing a second layer comprising a second III-V semiconductor material on the first layer, wherein:

the first III-V semiconductor material comprises gallium nitride (GaN);

the second III-V semiconductor material comprises aluminum gallium nitride (AlGaN);

the first gate structure is formed over the second III-V semiconductor material and between the first source region and the first drain region; and

the second gate structure is formed over the second III-V semiconductor material and between the second source region and the second drain region.